Texas Instruments, Dallas, TX

Email:    deepu@ti.com
Voice:    214.480.4619
Cell:       512.731.7755
Fax:       972.761.5063
 

Education

• Ph.D. in Computer Engineering, The University of Texas, Austin, Texas - August 2001.
• M.S. in Electrical Engineering, Villanova University, Villanova, Pennsylvania - August 1998.
• B.E. in Electronics and Communication Engineering, Andhra University, Visakhapatnam, India - June 1996.

Interests

• Computer Architecture
• Multimedia and DSP
• Workload Characterization (Performance Evaluation and Benchmarking)
• ASIC & FPGA Design

Professional Activities

• General Chair/Program co-Chair
  • 5^th IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems (ODES), March 11, 2007, San Jose, CA.
  • 4^th IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems (ODES), March 26, 2006, Manhattan, NY.
  • 3^rd IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems (ODES), March 20, 2005, San Jose, CA.
  • 2^nd IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems (ODES), March 21, 2004, San Jose, CA.
  • 1^st IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems (ODES), March 23, 2003, San Francisco, CA.
• Technical Program Committee member
  • 8^th IEEE Workshop on Media and Streaming Processors (MSP), December 9, 2006, Orlando, FL.
  • 2^nd IEEE Workshop on Unique Chips and Systems (UCAS), March 19, 2006, Austin, TX.
  • 1^st IEEE Workshop on Unique Chips and Systems (UCAS), March 20, 2005, Austin, TX.
  • IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 20-22, 2005, Austin, TX.
  • 7^th IEEE Workshop on Workload Characterization (WWC), October 25, 2004, Austin, TX.
  • IEEE Workshop on Signal Processing Systems (SIPS’04), October 13-15, 2004, Austin, TX.
  • 2^nd IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems (ODES), March 21, 2004, San Jose, CA.
  • 5^th IEEE Workshop on Media and Streaming Processors (MSP), December 1, 2003, San Diego, CA.
  • 6^th IEEE Workshop on Workload Characterization (WWC), October 27, 2003, Austin, TX.
  • 1^st IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems (ODES), March 23, 2003, San Francisco, CA.
• Registration Chair
  • 4^th IEEE Workshop on Workload Characterization (WWC), December 2, 2001, Austin, TX.
  • 3^rd IEEE Workshop on Workload Characterization (WWC), September 16, 2000, Austin, TX.
  • 2^nd IEEE Workshop on Workload Characterization (WWC), October 9, 1999, Austin, TX.
• Reviewer
(in addition to program committee assignments and not limited to)
• IEEE/ACM International Symposium on Computer Architecture (ISCA) - 2002
• IEEE/ACM International Symposium on Microarchitecture (MICRO) - 1999, 2000, and 2001
• IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) - 2000
• IEEE International Conference on Computer Design (ICCD) - 1999
• IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) - 2001
• IEEE International Symposium on High Performance Computer Architecture (HPCA) - 2000 and 2001
• IEEE Transactions on Computers
• IEEE Transactions on VLSI Systems
• IEEE Journal on Solid State Circuits
• Member
• IEEE (1996 - present), IEEE Computer Society, IEEE Signal Processing Society
• ACM, ACM - SIGARCH (2000 - 2007)

Publications (journals, conferences, workshops, and book chapters)

• D. Talla and J. Golston, "Using DaVinci^TM technology for digital video devices," IEEE Computer Magazine, vol. 40, no. 10, pp. 53-61, October 2007.
• D. Talla, "An innovative HD video and digital image processor for low-cost digital entertainment products," Proceedings of IEEE HOT Chips, August 19-21: 2007, Stanford University, California.
• D. Talla, "A reference design for a DaVinci^TM technology MPSoC targeting digital imaging consumer products," 7th International Forum on Application-Specific Multi-Processor SoC, June 25-29: 2007, Hyogo, Japan.
• A. Jerraya, O. Franza, M. Levy, M. Nakaya, P. Paulin, U. Ramacher, D. Talla, and W. Wolf, "Envisioning the future for multiprocessor SoC," Round table, IEEE Design&Test, vol. 24, no. 2, March/April 2007.
• D. Talla, "DaVinci^TM technology for digital video applications," 6th International Forum on Application-Specific Multi-Processor SoC, August 14-18: 2006, Estes Park, Colorado.
• D. Talla, C. Y. Hung, R. Talluri, F. Brill, D. Smith, D. Brier, B. Xiong, and D. Huynh, "Anatomy of a portable digital mediaprocessor," IEEE Micro, vol. 24, no.2, pp. 32-39, March/April 2004.
• D. Talla, R. Austen, D. Brier, C. Y. Hung, D. Huynh, D. Smith, B. Xiong, R. Talluri, and F. Brill, "TMS320DM310 - A portable digital media processor," Proceedings of IEEE HOT Chips, August 17-19: 2003, Stanford University, California.
• D. Talla and L. K. John, "Facts and myths about media processing on general-purpose processors," Proceedings of IEEE International Conference on Information Technology: Research and Education (Special Session on Technology and Trends in Media Processing), August 10-13: 2003, Newark, New Jersey. (Invited Paper)
• D. Talla, L. K. John, and D. Burger, "Bottlenecks in multimedia processing with SIMD style extensions and architectural extensions," IEEE Transactions on Computers, vol. 52, no. 8, pp. 1015-1031, ISSN 0018-9340, August 2003.
• R. Radhakrishnan, L. John, R. Bhargava, and D. Talla, "Improving Java performance in embedded and general-purpose processors," (chapter #5) in Java Microarchitectures, edited by N. Vijaykrishnan and M. Wolczko, pp. 79-104, Kluwer Academic publishers, ISBN 1-4020-7034-9, April 2002.
• D. Talla and L. K. John, "MediaBreeze: A decoupled architecture for accelerating multimedia applications," ACM Computer Architecture News, ACM Press, ISSN 0163-5964, pp. 62-67, vol. 29. no. 5, December 2001.
• D. Talla and L. K. John, "Cost-effective hardware acceleration of multimedia applications," Proceedings of IEEE International Conference on Computer Design, pp. 415-424, September 17-20: 2001, Austin, Texas.
• D. Talla and L. K. John, "A decoupled architecture for accelerating multimedia applications," Proceedings of Workshop on Memory Access Decoupled Architectures in conjunction with IEEE International Conference on Parallel Architectures and Compilation Techniques, September 8: 2001, Barcelona, Spain.
• D. Talla, "Architectural techniques to accelerate multimedia applications on general-purpose processors," Ph.D. thesis, Department of Electrical and Computer Engineering, The University of Texas, August 2001, Austin, Texas.
• D. Talla, L. K. John, V. Lapinskii and B. L. Evans "Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures," Proceedings of IEEE International Conference on Computer Design, pp. 163-172, September 17-20: 2000, Austin, Texas.
• R. Radhakrishnan, D. Talla and L. K. John, "Allowing for ILP in an Embedded Java Processor," Proceedings of  IEEE/ACM International Symposium on Computer Architecture, pp. 294-305, June 10-14: 2000, Vancouver, Canada.
• D. Talla and L. K. John, "Execution Characteristics of Multimedia Applications on a Pentium II Processor," Proceedings of  IEEE International Performance, Computing, and Communications Conference, pp. 516-524, Feb 20-22: 2000, Phoenix, Arizona.
• D. Talla and L. K. John, "Performance Evaluation and Benchmarking of Native Signal Processing," Proceedings of European Conference on Parallel Processing, Lecture Notes in Computer Science #1685, pp. 266-270, Aug 31-Sep 3: 1999, Toulouse, France.
• D. Talla, S. S. Rao and L. K. John, "An Evolutionary Computation Embedded IIR LMS Algorithm," Proceedings of International Conference on Signal Processing Applications and Technology, Nov 1-4: 1999, Orlando, Florida.
• D. Talla and L. K. John, "Quantifying the effectiveness of MMX in Native Signal Processing," Proceedings of  IEEE Mid-West Symposium on Circuits and Systems, pp. 18-21, Aug 8-11: 1999, Las Cruces, New Mexico.
• D. Talla, S. S. Rao and K. Chellapilla, "TMS320C40 Based Implementation of a Real-Time Adaptive IIR Filter," Proceedings of International Conference on Signal Processing Applications and Technology, pp. 133-137, Sep 14-17: 1997, San Diego, California.

Presentations (other than conference presentations above)

• February 13, 2006, "An Architecture for Digital Video, Image, and Audio Applications," College of Engineering Seminar, Andhra University, Visakhapatnam, India. (Invited Talk).
• March 4, 2005, "Digital Consumer Devices," TI-Purdue day, Purdue University, Indiana. (Invited Talk)
• October 12, 2001, "Bottlenecks in multimedia processing with SIMD-style extensions and architectural enhancements," Electrical and Computer Engineering Seminar, Villanova University, Villanova, Pennsylvania. (Invited Talk)
• November 19, 1999, "Exploiting Parallelism in DSP and Multimedia Applications using SIMD, VLIW and Superscalar Architectures," Telecommunications and Signal Processing Seminar, The University of Texas, Austin, TX.
(Invited Talk)

• June 21, 1999, "Exploiting SIMD Parallelism in DSP and Multimedia Algorithms using the AltiVec Technology," ACM International Conference on Supercomputing, Rhodes, Greece.