Dr. Xie got the IEEE Philadelphia Section Engineer of the Year Award 2024! Congratulation!
"Hardware circuits and systems design for post-quantum cryptography – A tutorial brief" was accepted by IEEE Trans. Circuits and Systems II,!
Jiafeng Xie, W. Zhao, H. Lee, D. B. Roy, and X. Zhang, “Hardware circuits and systems design for post-quantum cryptography – A tutorial brief,” IEEE Trans. Circuits and Systems II, pp.1-7, 2024, accepted.
"CASA: A compact and scalable accelerator for approximate homomorphic encryption" was accepted by IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES)!
P. He, S. C. Oliva Madrigal, C¸ . K. Koc¸, T. Bao, and Jiafeng Xie, “CASA: A compact and scalable accelerator for approximate homomorphic encryption,” IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), vol. 2024, no. 2, pp. 1-30, 2024, accepted.
The SAC Lab has signed Educational Partnership Agreement (EPA) with AFRL, Rome, NY.
The Security and Cryptography (SAC) Lab is an academic research lab at Villanova University, led by Prof. Jiafeng (Harvest) Xie. The SAC lab conducts research in a variety of deeply technical topics in Post-Quantum Cryptographic Engineering, Fully Homomorphic Encryption, Computer Arithmetic & Digital Design, Fault Detection and Hardware Security and Digitalization for Telemetry Systems.
EHardware accelerator design, implementation, and security analysis for post-quantum cryptography.
Accelerating different fully homomorphic encryption schemes/components on hardware platforms.
Novel computer arithmetic techniques and implementation strategies in large-scale computation systems.
Novel fault attack and detection methodologies for cryptographic circuits and hardware IP protection.
New digital design and acceleration techniques for sophisticated aeronautical telemetry systems.
2024
Jiafeng Xie, W. Zhao, H. Lee, D. B. Roy, and X. Zhang, IEEE Trans. Circuits and Systems II, pp.1-7, 2024.
P. He, S. C. Oliva Madrigal, C¸ . K. Koc¸, T. Bao, and Jiafeng Xie, IACR Transactions on Cryptographic Hardware and Embedded Systems(TCHES), vol. 2024, no. 2, pp. 1-30, 2024.
2023
T. Bao, P. He, S. Bai, and Jiafeng Xie, IEEE Trans. VLSI Systems, pp. 1-12, 2023.
T. Bao, P. He, Jiafeng Xie, and H S. Jacinto, ACM Trans. Reconfigurable Technology and Systems, pp. 1-22, 2023 (FPT’23-Journal Track).
P. He, T. Tu, Jiafeng Xie, and H S. Jacinto, IEEE Trans. VLSI Systems, vol. 31, no. 10, pp. 1551-1564, 2023.
P. He, T. Tu, C¸ . K. Koc¸, and Jiafeng Xie, IEEE Computer Architecture Letters, vol. 22, no. 1, pp. 57-60, 2023 (popular paper in IEEE Xplore).
Y. Tu, P. He, C¸ .K. Koc¸, and Jiafeng Xie, IEEE Trans. VLSI Systems, vol. 31, no. 6, pp. 892-896, 2023.
P. He, Y. Tu, T. Bao, L. Sousa, and Jiafeng Xie, IEEE Trans. VLSI Systems, vol. 31, no. 4, pp. 596-600, 2023.
Samuel Coulon, Pengzhou He, Tianyou Bao, Jiafeng Xie, 57th Asilomar Conference on Signals, Systems, and Computers, pp. 1-8, 2023.
P. He*, T. Bao*, Y. Tu, and Jiafeng Xie, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2023), pp. 114-120, 2023 (*: equal contribution).
P. He, Y. Tu, and Jiafeng Xie, IEEE International Symposium on Circuits and Systems-2023 (ISCAS’23), pp. 1-5, 2023.
P. He and J. Xie, International Symposium on Quality Electronic Design (ISQED), pp. 1-8, 2023.
2022
P. He, T. Bao, Jiafeng Xie, and M. Amin, ACM Trans. Reconfigurable Technology and Systems, vol. 15, no.3, pp. 1-23, 2022 (FPT’22-Journal Track).
Y. Zhong, A. Jain, M.T. Rahman, N. Adadi, Jiafeng Xie, and U. Guin, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 38, pp. 527–546, 2022.
J. Imãna*, P. He*, T. Bao, Y. Tu, and Jiafeng Xie IEEE Transactions on Circuits and Systems-I, 2022 (*: equal contribution).
B. J. Lucas, A. Alwan, M. Murzello, Y. Tu, P. He, A. J. Schwartz, D. Guevara, U. Guin, K. Juretus, and Jiafeng Xie IEEE Computer Architecture Letters, 2022 (popular paper in IEEE Xplore).
C. -Y. Lee, M. Zeghid, A. Sghaier, H. Y. Ahmed and Jiafeng Xie, IEEE Access, 2022.
S. Hussain, S. Ullah, I. Ali, Jiafeng Xie, and V. Inukollu, Computer Communications, vol. 181, pp. 116-131, 2022..
Jiafeng Xie, P. He, X. Wang, and J. Im˜ana, IEEE Trans. Emerging Topics in Computing, vol. 10, no. 2, pp. 1222-1228, 2022.
P. He, T. Bao, Y. Tu and Jiafeng Xie, IEEE International Conference on Computer Design (ICCD), pp. 525-528, 2022.
P. He, Y. Tu, A. Khalid, M. O’Neil, and Jiafeng Xie, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’22), pp. 1-6, 2022.
T. Bao, J. L. Im˜ana, P. He and Jiafeng Xie, CODES+ISSS, pp. 5-6, 2022.
T. Bao, P. He, and Jiafeng Xie IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 1-4, 2022.
Y. Tu, P. He, C. Lee, D. Chasaki, and Jiafeng Xie IEEE International Symposium on Circuits and Systems-2022 (ISCAS’22), pp. 1-5, 2022.
Y. Tu, P. He, U. Guin, and Jiafeng Xie, GOMACTech, pp. 1-6, 2022 (accepted for presentation).
Jiafeng Xie, P. He, and T. Bao, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2022, (poster).
2021
P. He, U. Guin, and Jiafeng Xie IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp. 1-13, 2021.
Jiafeng Xie, P. He, and C.Y. Lee IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2021.
P. He, C. Lee, and Jiafeng Xie NIST Third PQC Standardization Conference, pp. 1-16, 2021 (presentation).
Jiafeng Xie, P. He, and W. Wen Design Automation Conference (DAC), pp. 1-6, 2021
Previous
Jiafeng Xie, C. Lee, P. Meher, and Z.-H. Mao, IEEE Trans. VLSI Systems, vol. 27, no. 9, pp. 2119-2130, 2019.
J. Pan, C. Lee, A. Sghaier, M. Zeghid, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 27, no. 7, pp. 1614-1622, 2019.
C. Lee and Jiafeng Xie IEEE Trans. Circuits and Systems-I, vol. 66, no. 1, pp. 203-214, 2019.
Jiafeng Xie, P. Meher, X. Zhou, and J. Zhang IEEE Trans. Multiscale Computing Systems, vol. 4, no. 4, pp. 773-783, 2018.
Z. Hu and Jiafeng Xie Symmetry, vol. 10, no. 11, pp. 1-11, 2018.
C. Lee, C. Fan, Jiafeng Xie, and S. Yuan IEEE Access, 6: 38234-38242, 2018.
Q. Shao, Z. Hu, S. Basha, Z. Zhang, Z. Wu, C.Y. Lee, and Jiafeng Xie IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 65, no. 8, pp. 2455-2465, 2018.
M. Kermani, A. Jalali, R. Azarderakhsh, Jiafeng Xie, and K.K. R. Choo IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, vol. 37, no. 3, pp. 696-704, 2018.
Jiafeng Xie, P.K. Meher, M. Sun, Y. Li, B. Zeng, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 64, no. 7, pp, 1815-1825, 2017.
Q. Shao, Z. Hu, S. Chen, P. Chen, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 25, no. 10, pp. 2817-2827, 2017.
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 3, pp. 881-890, 2015.
P. Chen, N. Basha, M. Kermani, R. Azarderakhsh, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 25, no. 9, pp. 725-734, 2017.
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 62, no. 5, pp. 481-485, 2015.
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 1, pp. 110-119, 2015.
Jiafeng Xie, J. He, and P.K. Meher IEEE Trans. Computers, vol. 62, no. 6, pp. 1170-1178, 2013.
Jiafeng Xie, P.K. Meher, and J. He IEEE Trans. VLSI Systems, vol. 21, no. 1, pp. 168-172, 2013.
Jiafeng Xie, J. He, and G. Tan Microelectronics Journal (Elsevier), vol. 41, no. 6, pp. 365-370, 2010.
Jiafeng Xie, J. He, and P.K. Meher IEEE Trans. VLSI Systems, vol. 21, no. 2, pp. 385-389, 2013.
Jiafeng Xie, J. He, and W. Gui Journal of Central South University of Technology, vol. 21, no. 5, pp. 1283-1289, 2012.
J. He, Jiafeng Xie, and M. He Journal of Convergence Information Technology, vol. 6, no. 5, pp. 305-313, 2011.
J. He and Jiafeng Xie Journal of Computers, vol. 6, no. 11, pp. 2376-2381, 2011.
Jiafeng Xie and G. Tan Journal of Zhongyuan University of Technology, vol. 21, no. 2, pp. 72-75, 2010.
Jiafeng Xie and G. Tan PLC&FA, vol. 6, no. 1, pp. 668-671, 2009.
Jiafeng Xie, K. Basu, Kris, M. Gaj, and U. Guin IEEE VLSI Testing Symposium (VTS), pp. 1-10, 2020 (invited).
C. Lee and Jiafeng Xie Asia and South Pacific Design Automation Conference (ASPDAC), pp. 1-6, 2020.
C. Lee and Jiafeng Xie IEEE International Conference on Computer Design (ICCD), pp. 1-9, 2019.
C. Lee and Jiafeng Xie IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 21-30, 2019 (Best Paper Award).
Jiafeng Xie, C. Lee, and P. K. Meher IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
Jiafeng Xie and C. Lee ACM Great Lakes Symposium on VLSI (GLVLSI), 2019.
Jiafeng Xie and C. Lee ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
C. Lee and Jiafeng Xie IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2018.
Jiafeng Xie and X. Zhou IEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2017.
S. Chen, P. Chen, Q. Shao, S. Basha, and Jiafeng Xie Asia Conference on Power and Electrical Engineering (ACPEE), pp. 1-6, 2017.
M. Kermani, R. Azarderakhsh, and Jiafeng XieIEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2016.
D.V. Penumetcha, Jiafeng Xie, and S. Ren, IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, 2015.
Jiafeng Xie, P.K. Meher, and J. He, IEEE International Symposium on Circuits and Systems-2012, ISCAS-12, pp. 89-92, 2012.
...
Others
Jiafeng Xie, SIGDA Electronic Newsletter, “What is” Column, May 2021. [Online]. Available: https://www.sigda.org/publications/newsletter/
Engineer of the Year Award
IEEE Philadelphia Section, 2024
Art Ryan Award
ECE Department, Villanova University, 2023
Tenure Track Faculty Career Development Award
College of Engineering, Villanova University, 2023
AFRL VFRP Award and Extension Award
AFRL, Rome, NY, 2022
Merrill Buckley Jr. Student Project Award
IEEE Philadelphia Section, 2022
Brian Anderson Memorial Award
ECE Department, Villanova University, 2022
Best Paper Award
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019
You are free to use the resources shared below if used for non-profit purposes or open source projects. Please quote resources in the project from Villanova University Security & Cryptography Lab. :)
The SAC Lab is not responsible for the correctness of the source code.
Source code for the polynomial multiplication (Fig. 3) presented in the paper of "Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary Ring-LWE post-quantum cryptography"
Source code for the low complexity and high speed architectures presented in the paper of "Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator"
Source code for the two architectures presented in the paper of "Efficient hardware arithmetic for inverted Binary Ring-LWE based post-quantum cryptography"