Xun Jiao

Assistant Professor
Department of Electrical and Computer Engineering
Villanova University

Office: Tolentine 415
Email: xun.jiao@villanova.edu
News

[Update] For more news, please visit my group website.
[01/2019] Serve on Program Committee at ICESS 2019! Please consider to submit!
[12/2018] Serve as Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD)!
[12/2018] Serve on Program Committee in LCTES 2019. Please consider to submit!
[11/2018] Serve on Program Comittee in International Conference on Omni-layer Intelligent Systems. Please consider submit!
[10/2018] Co-organize a special session on dependable cyber-physical system in IEEE International Conference on Cyber Physical and Social Computing (CPSCOM-2019). Please consider submit!
[08/2018] Joined ECE department of Villanova University as tenure-track assistant professor this fall. I am looking for self-motivated Ph.D. students to join my group working on energy-efficient machine learning accelerator. For more information, please look here.
[06/2018] Presented my PhD thesis in DAC PhD forum!
[06/2018] Graduated with a Ph.D. degree from UC San Diego!



Biography

I have been an assistant professor in ECE department of Villanova University since 2018. I lead Dependable, Efficient, and Intelligent Computing Lab (DETAIL) at Villanova University.

Before that, I obtained my Ph.D. degree from the department of Computer Science and Engineering at the University of California, San Diego in 2018. I earned a first class Bachelor degree in Telecommunication Engineering with Management from BUPT-QMUL Joint Programme held jointly by Beijing University of Posts and Telecommunications and Queen Mary, University of London, in 2013.

My research interests are in the general area of computer engineering, with focus on approximate computing, deep learning accelerator, energy-efficient computing systems, software-hardware codesign, and test of integrated circuits, embedded system, and computer architecture.

I am an Associate Editor in of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Guest Editor of Journal of System Architecture, Session Co-Chair of IEEE CPSCOM, Program Committee of LCTES, ICESS, COINS. I have served as reviewers for TCAD, JETCAS, TCPS, TII, FGCS, TVLSI, TODAES, DAC, MASCOTS.




Publications

Journal:

Xun Jiao, Abbas Rahimi, Yu Jiang, Jianguo Wang, Hamed Fatemi, Jose Pineda de Gyvez, and Rajesh Gupta
CLIM: A Cross-level Workload-aware Timing Error Prediction Model for Functional Units. [PDF]
IEEE Transactions on Computers (TC) 2018 .

  • Yu Jiang , Hehua Zhang , Xiaoyu Song, Xun Jiao, William N. N. Hung, and Jiaguang Sun.
    Bayesian Network Based Reliability Analysis of PLC Systems. [PDF]
    IEEE Transaction on Industry Electronics (TIE) 2013.

  • Xibing Zhao, Hehua Zhang, Yu Jiang, Songzheng Song, Xun Jiao, and Ming Gu.
    An Effective Heuristic Based Approach for partitiong. [PDF]
    Hindawi, Journal of Applied Mathematics, 2013.

  • Conference:

  • Xun Jiao, Vahideh Akhlaghi, Yu Jiang, and Rajesh Gupta
    Energy-Efficient Neural Networks using Approximate Computation Reuse. [PDF]
    in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Dresden, Germany, 2018 .

  • Mingzhe Wang, Jie Liang, Yuanliang Chen, Yu Jiang, Xun Jiao, Han Liu, Xibin Zhao, Jiaguang Sun
    SAFL: increasing and accelerating testing coverage with symbolic execution and guided fuzzing. [PDF]
    in Proc. International Conference on Software Engineering (ICSE-Tool), Gothenburg, Sweden, 2018 .

  • Xun Jiao, Mulong Luo, Jeng-Hau Lin, and Rajesh Gupta
    An Assessment of Vulnerability of Hardware Neural Networks to Dynamic Voltage and Temperature Variations. [PDF]
    in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Irvine, USA 2017 .

  • Xun Jiao, Vincent Camus, Mattia Cacciotti, Yu Jiang, Christian Enz, and Rajesh Gupta
    Combining Structural and Timing Error in Overclocked Inexact Speculative Adders. [PDF]
    in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Lausanne, Switzerland 2017 .

  • Xun Jiao, Yu Jiang, Abbas Rahimi, and Rajesh Gupta
    SLoT: A Supervised Learning Model to Predict Dynamic Timing Errors of Functional Units. [PDF]
    in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Lausanne, Switzerland 2017 .

  • Xun Jiao, Yu Jiang, Abbas Rahimi, and Rajesh Gupta
    WILD: A Workload-Based Learning Model to Predict Dynamic Delay of Functional Units. [PDF]
    in Proc. IEEE International Conference on Computer Design (ICCD), Phoenix, USA 2016 .

  • Xun Jiao, Abbas Rahimi, Balakrishnan Narayanaswamy, Hamed Fatemi, Jose Pineda de Gyvez, and Rajesh Gupta.
    Supervised Learning Based Model for Predicting Variability-Induced Timing Errors. [PDF]
    in Proc. IEEE International NEW Circuits And Systems (NEWCAS) conference, Grenoble, France 2015

  • Yu Jiang, Hehua Zhang, Xun Jiao, Xiaoyu Song, William N.Hung, Ming Gu, and Jiaguang Sun.
    Uncertain Model and Algorithm for Hardware/Software Partitioning. [PDF]
    in Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI),2012.

  • Hehua Zhang, Yu Jiang, Xun Jiao, Xiaoyu Song, William N.Hung, and Ming Gu.
    Reliability Analysis of PLC Systems by Bayesian Network. [PDF]
    in Proc. International Conference on Software Security and Reliability (SERE) 2012 .