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\def\classTime{{"TR 10:00 - 11:15 AM (Section 001) or 1:00 - 2:15 PM (Section 002)",""}}
\def\classRm{{"Tolentine Hall 418",""}}
\def\classLive{{"",""}}
\def\classInstructor{{"Xiaofang Maggie Wang",""}}
\def\classInstrContact{{"Blackboard: elearning.villanova.edu",""}}
\def\classInstrOffHrs{{"TR 11:50  AM - 12:50 PM",""}}
\def\classInstrLive{{"",""}}
\def\labTime{{"F 09:00 - 11:00 AM (Section 001) or 12:30 - 2:20 PM (Section 002)",""}}
\def\labRm{{"CEER 206",""}}
\def\labLive{{"",""}}
\def\labInstructor{{"Edward Hepler",""}}
\def\labInstrContact{{"Blackboard: elearning.villanova.edu",""}}
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\newcommand\semester{Fall 2021}
\newcommand\rsemester{202220}
\newcommand\courseNum{ECE 3445}
\newcommand\courseName{Computer Architecture}
\newcommand\courseCoordinator{X. Maggie Wang}
\newcommand\credits{4}
\newcommand\contactHrs{5}
\newcommand\lecture{1}
\newcommand\lab{1}
\newcommand\undergradCourse{1}
\newcommand\isFreshmanCourse{0}
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\newcommand\meetingDesc{Two 75-minute lectures and a 110-minute lab meeting}
\newcommand\meetingMisc{Special notes on meeting info go here, if specified}
\newcommand\instructorMisc{Special notes on instructor(s), TA(s) go here, if specified}
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\newcommand\textBookTitle{Computer Organization and Design MIPS Edition: The Hardware/Software Interface (5th Edition)}
\newcommand\textBookAuth{David A. Patterson and John L. Hennessy}
\newcommand\textBookPub{Morgan Kaufmann}
\newcommand\textBookYr{2013}
\newcommand\textBookISBN{9780124077263}
\newcommand\supplMaterials{References will be posted in blackboard.}
\newcommand\refPapers{References go here, if specified}
\newcommand\textBookMisc{Special notes on textbook(s) go here, if specified}
\newcommand\catalogDesc{Computer architecture is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance, power, and cost goals. This course examines in-depth the inner-workings of modern computer hardware design and the design tradeoffs at the hardware-software interface. The MIPS processor is employed as an example throughout the course. The topics include instruction set architecture, MIPS assembly programming, integer and floating-point arithmetic circuits, processor datapath and control design, pipelining, memory hierarchy, I/O and storage devices, multi-core processor design, etc. 
An integral component of this course will be a sequence of hands-on hardware laboratory assignments where you will step-by-step design and implement the single-cycle and pipelined 32-bit MIPS processors. The Altera DE10 FPGA development board, and Quartus and ModelSim will be used in the lab for you to design, build and test the processors. 
}
\newcommand\preReqs{ECE 2042 \& 2043, ECE 2044 \& 2045}
\newcommand\coReqs{None}
\newcommand\coreRequirement{}
\newcommand\courseExpectation{After a successful completion of the course, the student will understand from the engineering's perspective how a computer hardware system works and will be able to design and implement pipelined processors and their basic peripherals from basic logic gates on an FPGA board. Students will also be able to understand and evaluate various factors that affect computer system performance.}
\newcommand\ABETOutOne{1}
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\newcommand\covTopics{\item Course overview
\item Computer technology evolution
\item Instruction set architecture (ISA) overview
\item MIPS processor instruction set
\item Binary addition/subtraction
\item ALU design
\item Sequential and parallel multipliers
\item Floating-point arithmetic
\item Understanding computer performance
\item Single-cycle MIPS processor: Datapath 
\item Single-cycle MIPS processor: Control
\item Multi-cycle MIPS processor: Datapath
\item Multi-cycle MIPS processor: Control
\item Ideal pipelined MIPS processor datapath and control
\item Pipelining: data hazards and solutions
\item Pipelining: branch hazards and solutions
\item Memory introduction and memory technologies
\item Cache 
\item Virtual memory 
\item Introduction to parallel computer architecture
}
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\newcommand\scheduleRows{15}
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\newcommand\schedule{\begin{table}[h!] \centering 
\caption*{Tentative Schedule for \textbf{All Sections}} \vspace{0.05in}
{\renewcommand{\arraystretch}{1.5} \small
\begin{tabularx}{\linewidth}{c|l|X|X}
\toprule
\large \textbf{Date} & \large \textbf{Topics} & \large \textbf{Homework Assignment} & \large \textbf{Textbook}\\
\midrule \midrule
Aug. 24 \& 26 & Introduction & None & \\
Aug. 31 \& Sept. 02 & Stuff... & HW1 & \\
... &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
 &  &  & \\
\bottomrule \end{tabularx} } \end{table}}
\newcommand\gradingPolicy{Homework assignments:  20% \\
Lab: 30% \\
Midterm 20%\\
Final 30%\\

\\
\\
Letter grade scale: A(93--100), A--(90--92), B+(87--89), B(83--86), B--(80--82), C+(77--79),\\
C(73--76), C--(70--72), D+(67--69), D(63--66), D--(60--62), F(<60)}
\newcommand\HWandLabPolicy{Weekly homework assignments will be posted in the blackboard, and are normally due by the end of day on Tuesday unless announced otherwise. Please scan your homework solutions into a dingle PDF file, and submit it in the blackboard. Please include your last name in the name of the PDF file, e.g. HW1-Wang. 

You will lose 20% of homework points for each school day if failing to submit homework on time.

The specific information related to lab requirements can be found through the lab folders in Blackboard.}
\newcommand\AttendancePolicy{\textcolor{red}{Students are expected to attend all the class meetings and are responsible for all the materials covered in class including handouts and class notes. Sudents should inform the instructor if they plan to be late or absent from class.  }}
\newcommand\ElectronicsPolicy{\textcolor{red}{Since you opted for a customize electronics policy, you should edit this part. Your policy should address your general stance on recording of class sessions and the circumstances under which recording will be allowed or prohibited. If you generally prohibit recording, yet allow recording of certain classes for some reason, then ypu should notify all students that those classes will be recorded. If recording is permitted as an ADA accommodation for a student, you obviously should not identify that student(s).)}}
