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\def\classTime{{"Wednesday from 12:00 pm to 02:30 pm",""}}
\def\classRm{{"in CEER 314",""}}
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\def\classInstructor{{"Xiaofang Maggie Wang",""}}
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\def\classInstrOffHrs{{"TR 11:50 AM - 12:50 PM",""}}
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\newcommand\semester{Fall 2021}
\newcommand\rsemester{202220}
\newcommand\courseNum{ECE 8455}
\newcommand\courseName{Advanced Digital Design Using FPGAs}
\newcommand\courseCoordinator{Xiaofang Maggie Wang}
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\newcommand\meetingMisc{Special notes on meeting info go here, if specified}
\newcommand\instructorMisc{Special notes on instructor(s), TA(s) go here, if specified}
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\newcommand\supplMaterials{There is no particular textbook required as I will be integrating materials from many sources. However, a comprehensive VHDL reference book is required. If you do not have one, the following book is recommended.         

A VHDL Primer, 3rd edition, J. Bhasker, Prentice Hall, 1999, ISBN: 0-13-096575-8.
}
\newcommand\refPapers{1. Advanced FPGA Design: Architecture, Implementation, and Optimization, by S. Kilts

2. Technical documentation in the course References folder
}
\newcommand\textBookMisc{Special notes on textbook(s) go here, if specified}
\newcommand\catalogDesc{Introduces students to advanced digital design and implementation using FPGAs (Field-Programmable Gate Arrays). Topics include VHDL \& Verilog, FPGA architectures, programming technologies, design methodologies, simulation and synthesis, place and route, and timing analysis, which board and EDA tools are used to help students gain hands-on experience. Prerequisite: Digital/logic design and VHDL basics.}
\newcommand\preReqs{Digital logic design and VHDL basics (VU ECE 2042 \& ECE 2043 or equivalent courses).}
\newcommand\coReqs{None}
\newcommand\coreRequirement{}
\newcommand\courseExpectation{An FPGA (Field-Programmable Gate Array) device is a semi-custom integrated circuit (IC) that contains an array of programmable (configurable) logic blocks and programmable (configurable) interconnects that connect the logic blocks. FPGAs have undergone phenomenal advances in capacity and complexity during the past few years, and have transformed into most flexible and domain-specific platforms for many applications. Such advances, along with the skyrocketing costs of nano silicon processes and the ever-shrinking time-in-market window continue to successfully help FPGAs erode ASIC and ASSP market shares.
The objective of this course is to introduce students to advanced digital design using VHDL/Verilog for FPGAs. We start with fundamental concepts of FPGAs and focus on practical aspects of FPGA-based digital design later on. Students will learn various FPGA design approaches, such as HDL-, schematic-, and C/DSP-based methods. The final segment of the class covers special topics that identify current trends in FPGA technologies. The design and implementation tools used throughout the course include Quartus Prime and ModelSim. Hands-on experience is gained by implementing various designs and a comprehensive project on an Intel (Altera) FPGA development board. Please check the course schedule of topics for more details. 
}
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\newcommand\covTopics{\item \textcolor{blue}{\textbf{Please refer to the schedule of topics below.}}}
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\newcommand\schedule{\begin{table}[h!] \centering 
\caption*{Tentative Schedule for \textbf{All Sections}} \vspace{0.05in}
{\renewcommand{\arraystretch}{1.5} \small
\begin{tabularx}{\linewidth}{c|l}
\toprule
\large \textbf{Date} & \large \textbf{Topics}\\
\midrule \midrule
08/25 & Course Overview; Introduction to FPGAs\\
09/01 & FPGA design methodology and tools; Quartus Prime Tutorial 1\\
09/08 & VHDL 1: Hardware modeling basics; 
Tutorial: Basic ModelSim simulation
\\
09/15 & Introduction to Verilog\\
09/22 & VHDL 2: Behavior modeling\\
09/29 & VHDL 3: FSM and advanced topics\\
10/06 & Testbench;  Design Examples: Audio codec 
Tutorial: Advanced ModelSim simulation\\
10/13 & \textcolor{blue}{Fall Break}\\
10/20 & \textcolor{red}{Midterm exam}\\
10/27 & Memory designs for FPGA-based systems\\
11/03 & Lab and project help\\
11/10 & VHDL/Verilog codling style for synthesis optimizations\\
11/17 & Optimizing performance by driving FPGA synthesis tools\\
12/01 & FPGA power analysis, reset and clock circuits, and timing issues\\
12/08 & \textcolor{red}{Project Presentation}\\
\bottomrule \end{tabularx} } \end{table}}
\newcommand\gradingPolicy{1.	Homework Assignments -- 50\%

2.	Final exam -- 25\%

3.	Project: 25\%

Letter grade scale: A(94--100), A--(90--93), B+(87--89), B(83--86), B--(78--82), C+(74--77),\\
C(70--73), F(<70)}
\newcommand\HWandLabPolicy{Weekly homework assignments will be posted in the Blackboard and due the following week, unless announced otherwise. 

Learning how to look for appropriate technical documentation, read and understand them efficiently in a focused manner is one of the essential engineering skills, and one of the objectives of the course. You are expected to develop debug skills through vendor’s technical documentation and discussion forums when you have questions and problems with the assignments and project. In addition to the lectures, additional reading assignments will be posted on the course web as needed.}
\newcommand\AttendancePolicy{\textcolor{blue}{You are expected to attend all the class meetings and are responsible for all the material covered in class including handouts and class notes. }}
\newcommand\ElectronicsPolicy{\textcolor{red}{Since you opted for a customize electronics policy, you should edit this part. Your policy should address your general stance on recording of class sessions and the circumstances under which recording will be allowed or prohibited. If you generally prohibit recording, yet allow recording of certain classes for some reason, then ypu should notify all students that those classes will be recorded. If recording is permitted as an ADA accommodation for a student, you obviously should not identify that student(s).)}}