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\newcommand\semester{Spring 2022}
\newcommand\rsemester{202230}
\newcommand\courseNum{ECE 8405}
\newcommand\courseName{Computer Organ \& Design}
\newcommand\courseCoordinator{Edward L. Hepler}
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\newcommand\meetingDesc{One 2 hour 40 minute lecture/lab per week}
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\newcommand\textBookTitle{Computer Organization and Design RISC-V Edition, The Hardware Software Interface, Second Edition}
\newcommand\textBookAuth{David A. Patterson \& John L. Hennessy}
\newcommand\textBookPub{Elsevier}
\newcommand\textBookYr{2021}
\newcommand\textBookISBN{978-0-12-820331-6}
\newcommand\supplMaterials{Provided via Blackboard}
\newcommand\refPapers{References go here, if specified}
\newcommand\textBookMisc{Special notes on textbook(s) go here, if specified}
\newcommand\catalogDesc{Computer components, subsystems, and their interaction. Instruction sets, central processing units, microprogramming, intersystem communications, interrupts, DMA, memory hierarchy, and operating system demands on hardware. Prerequisite: Undergraduate background in digital systems (equivalent to ECE 2042).}
\newcommand\preReqs{Undergraduate level background in digital systems; Understanding of the C programming language}
\newcommand\coReqs{None}
\newcommand\coreRequirement{}
\newcommand\courseExpectation{Introduce the basic concepts of Computer Organization through both lecture and simulation.
Use VHDL to model computer systems}
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\newcommand\covTopics{\item Logic and Computer Arithmetic Review
\item Classification of machines
\item Instruction Set Architecture
\item Non-pipelined Processor Implementation
\item Pipelined Processor Implementation
\item Branching Techniques
\item Memory Hierarchy
\item Caches
\item Memory Management}
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1, 2 & Introduction; Review; VHDL; Simulation & VHDL; Adder Model/Simulation\\
3 & Machine classification; ISA & Register File; Synthesis\\
4 & Software; Stack; OS; Testbenches & C Compile; Memories\\
5 & Instruction Formats; RISC-V ISA & ALU; Shifter\\
6, 7 & Non-pipelined Implementation & DataPath; Control; Testbench\\
8, 9 & Pipelined Implementation & Pipelining\\
10 & Memory Hierarchy; Caches & Pipelining\\
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Letter grade scale: A(94--100), A--(90--93), B+(87--89), B(83--86), B--(78--82), C+(74--77),\\
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