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\def\classTime{{"TR from 02:30 pm to 03:45 pm in Drosdick Hall 036.",""}}
\def\classRm{{"Drosdick 036",""}}
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\def\classInstructor{{"Samir Talegaon",""}}
\def\classInstrContact{{"Blackboard: elearning.villanova.edu",""}}
\def\classInstrOffHrs{{"TR 11:00 AM - 1:00 PM",""}}
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\newcommand\semester{Fall 2025}
\newcommand\rsemester{202620}
\newcommand\courseNum{ECE 3170}
\newcommand\courseName{Computer Architecture}
\newcommand\courseCoordinator{Samir Talegaon}
\newcommand\credits{3}
\newcommand\contactHrs{3}
\newcommand\lecture{1}
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\newcommand\meetingDesc{Two 75-minute lectures}
\newcommand\meetingMisc{Special notes on meeting info go here, if specified}
\newcommand\instructorMisc{Special notes on instructor(s), TA(s) go here, if specified}
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\newcommand\textBookTitle{Computer Organization and Design MIPS Edition: The Hardware/Software Interface (6th Edition)}
\newcommand\textBookAuth{David A. Patterson and John L. Hennessy}
\newcommand\textBookPub{Morgan Kaufmann}
\newcommand\textBookYr{2020}
\newcommand\textBookISBN{9780128201091}
\newcommand\supplMaterials{References will be posted in blackboard.}
\newcommand\refPapers{References go here, if specified}
\newcommand\textBookMisc{Special notes on textbook(s) go here, if specified}
\newcommand\catalogDesc{Computer architecture is the science and engineering of selecting and interconnecting hardware components to create a computer that meets functional, performance, power, and cost goals. This course examines in-depth the inner-workings of modern computer hardware design and the design tradeoffs at the hardware-software interface. The MIPS processor is employed as an example throughout the course. The topics include instruction set architecture, MIPS assembly programming, integer and floating-point arithmetic circuits, processor datapath and control design, pipelining, memory hierarchy, I/O and storage devices, multi-core processor design, etc. An integral component of this course will be a sequence of hands-on hardware laboratory assignments where you will step-by-step design and implement the single-cycle and pipelined 32-bit MIPS processors. The Intel (Altera) DE10-Standard FPGA development board, and Quartus and ModelSim will be used in the lab for you to design, build and test the processors.}
\newcommand\preReqs{ECE 2170 and ECE 2172 and ECE 2173}
\newcommand\coReqs{ECE 3171}
\newcommand\coreRequirement{}
\newcommand\courseExpectation{After a successful completion of the course, the student will\\
1. understand from the engineering's perspective how a computer hardware system works.\\
2. be able to analyze the instruction set architecture of a given processor and apply to future processor design.\\
3. be able to design and implement major processor components from scratch, and integrate them to form a pipelined processor. \\
4. be able to measure computer performance and analyze how it is affected by various design parameters. \\
5. be able to apply engineering skills developed through hands-on lab experiments to future digital system design.\\
}
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\newcommand\covTopics{\item Course overview
\item Computer technology evolution
\item Instruction set architecture (ISA) overview
\item MIPS processor instruction set
\item Binary addition/subtraction
\item ALU design
\item Sequential and parallel multipliers
\item Floating-point arithmetic
\item Understanding computer performance
\item Single-cycle MIPS processor: Datapath 
\item Single-cycle MIPS processor: Control
\item Multi-cycle MIPS processor: Datapath
\item Multi-cycle MIPS processor: Control
\item Ideal pipelined MIPS processor datapath and control
\item Pipelining: data hazards and solutions
\item Pipelining: branch hazards and solutions
\item Memory introduction and memory technologies
\item Cache 
\item Virtual memory 
\item Introduction to parallel computer architecture
}
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\newcommand\gradingPolicy{Homework assignments:  25\% 

Tests: 20\% X 2

Final exam: 30\%

Participation: 5\%
\\
\\
Letter grade scale: A(93--100), A--(90--92), B+(87--89), B(83--86), B--(80--82), C+(77--79),\\
C(73--76), C--(70--72), D+(67--69), D(63--66), D--(60--62), F(<60)}
\newcommand\HWandLabPolicy{Weekly homework assignments will be posted in the blackboard, and are normally due by the end of day on Tuesday unless announced otherwise. Please scan your homework solutions into a single PDF file, and submit it in the blackboard. Please include your last name in the name of the PDF file, e.g. HW1-Talegaon.pdf. 

Late homework submissions will lose 10\% of the assigned points per each school day. No late homework submission will be accepted five school days after the due day. 

}
\newcommand\AIPolicy{\textcolor{red}{
The use of AI-generated content is not permitted in this course.
Its use will result in an academic integrity violation and a zero on the assignment.\\
}}
\newcommand\AttendancePolicy{\textcolor{red}{Students are expected to attend all the class meetings and are responsible for all the materials covered in class including handouts and class notes.}}
\newcommand\ElectronicsPolicy{\textcolor{red}{
Since you opted for a customize electronics policy, you should edit this part. Your policy should address your general stance on recording of class sessions and the circumstances under which recording will be allowed or prohibited. If you generally prohibit recording, yet allow recording of certain classes for some reason, then you should notify all students that those classes will be recorded. If recording is permitted as an ADA accommodation for a student, you obviously should not identify that student(s).
}}
