\setcounter{numTAs}{0}
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\def\secNum{{"001","DL1",""}}
\def\tenSchFileName{{"","",""}}
\def\classTime{{"Wednesday from 03:00 pm to 05:30 pm","Wednesday from 03:00 pm to 05:30 pm in Online SYN.",""}}
\def\classRm{{"CEER 109","Virtual",""}}
\def\classLive{{"","",""}}
\def\classInstructor{{"Jiafeng Xie","Jiafeng Xie",""}}
\def\classInstrContact{{"","",""}}
\def\classInstrOffHrs{{"Tuesday 2-4pm (can be zoom format)","Tuesday 2-4pm (can be zoom format)",""}}
\def\classInstrLive{{"","",""}}
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\newcommand\semester{Fall 2023}
\newcommand\rsemester{202420}
\newcommand\courseNum{ECE 8440}
\newcommand\courseName{Hardware System Design \& Modeling}
\newcommand\courseCoordinator{Jiafeng Xie}
\newcommand\credits{3}
\newcommand\contactHrs{3}
\newcommand\lecture{1}
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\newcommand\meetingDesc{One 150-minute lecture}
\newcommand\meetingMisc{Special notes on meeting info go here, if specified}
\newcommand\instructorMisc{Special notes on instructor(s), TA(s) go here, if specified}
\newcommand\textBookExists{0}
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\newcommand\supplMaterials{\\
1. Book: Arithmetic Circuits for DSP Applications, by P. K. Meher and T. Stouraitis, Wiley-IEEE Press, 2017.

2. Book: Introduction to Logic Circuits \& Logic Design with VHDL, by Brock J. LaMeres, 2nd ed., Springer, 2019.

3. Course slides
}
\newcommand\refPapers{1. Book: VLSI Digital Signal Processing Systems: Design and Implementation, by K. K. Parhi, John Wiley \& Sons, 2015}
\newcommand\textBookMisc{Special notes on textbook(s) go here, if specified}
\newcommand\catalogDesc{Introduces the concepts, skills, and techniques related to hardware design and modeling, including advanced computer arithmetic, system-to-hardware mapping techniques, memory-based design, pipeline/systolic processing, application-specific hardware accelerator design, and large-scale VHDL coding and testing skills.}
\newcommand\preReqs{None}
\newcommand\coReqs{None}
\newcommand\coreRequirement{For CPE/EE graduate students (or similar level) who are interested in hardware design}
\newcommand\courseExpectation{Be able to understand and apply hardware design knowledge into practical systems, can model, design, and implement specific systems according to specific requirements. More importantly, prepare oneself as a qualified engineer for life-long learning and catch up rapid trend in technology advancing.

1.	Be able to collaborate and communicate with classmates for projects and homework.

2.	Be able to use FPGA synthesis tools to design, synthesize, and implement large-scale hardware systems including use HDL for mapping processing algorithms into hardware architectures, test and validate the correctness of the hardware design, and implement the designs on FPGAs.

3.	Understand and learn advanced computer arithmetic.

4.	Be able to use memory-based techniques to design digital processing system.

5.	Familiar with pipeline and systolic processing design skills.

6.	Be able to design an application-specific hardware accelerator while taking care of the system constraints and requirements like processing time, power consumption, cost and size along with the possible trade-off considerations.
}
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\newcommand\covTopics{\item Introduction, Motivation \& Review of Basics
\item Advanced Computer Arithmetic-I: Integer and Modular Arithmetic
\item System-to-Hardware Mapping-I: Point-Wise Operations (PWM)
\item Advanced Computer Arithmetic-II: Modulo Reduction Arithmetic
\item System-to-Hardware Mapping-II: Accumulation
\item Advanced Computer Arithmetic-III: Circulant Arithmetic
\item Memory-based Design-I: Modern Storage Unit
\item Memory-based Design-II: Memory Implementation
\item Systolic Design: Overview and Architecture
\item Large-scale VHDL Coding and Testing
\item Application-Specific Hardware Accelerator-I (Discuss Existing Research Outcomes)
\item Application-Specific Hardware Accelerator-II}
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\newcommand\schedule{\begin{table}[h!] \centering 
\caption*{Tentative Schedule for \textbf{All Sections}} \vspace{0.05in}
{\renewcommand{\arraystretch}{1.5} \small
\begin{tabularx}{\linewidth}{c|c|c|c}
\toprule
\large \textbf{Month} & \large \textbf{Date} & \large \textbf{Course Topic} & \large \textbf{Homework/Project}\\
\midrule \midrule
August & 23rd & Introduction, Motivation \& Review of Basics & \\
August & 30th & Computer Arithmetic-I & HW-1: VHDL for adder\\
September & 6th & System-to-Hardware Mapping-I & \\
September & 13rd & Computer Arithmetic-II & Project-1: Longa Reduction\\
September & 20th & System-to-Hardware Mapping-II & \\
September & 27th & Computer Arithmetic-III & HW-2: Accumulator \& PWM\\
October & 4th & Mid-Term Exam & \\
 &  & Fall Break (9th-15th) & \\
October & 18th & Memory-based Design-I & HW-3: Memory features\\
October & 25th & Memory-based Design-II & \\
November & 1st & Systolic Design & Project-2: Memory Implementation\\
November & 8th & Large-scale VHDL Coding & \\
November & 15th & Application-Specific Hardware Accelerator-I & Project-3 (Final Project)\\
November & 29th & Application-Specific Hardware Accelerator-II & \\
December & 6th & Final Project Presentation & \\
\bottomrule \end{tabularx} } \end{table}}
\newcommand\gradingPolicy{Note: each class is also accompanied with VHDL teaching, its schedule can be seen in the slides of week-1.

\\
Your final grade will be determined from the following:

•	Homework*: 15%

•	Project**40%

•	Mid-Term Exam***: 15%

•	Final Project****: 30%

*: Each homework will be 5 points, total 15 points.

**: There will be 2 regular projects (each 20points), total 40 points.

***: Exam review will be provided and the schedule can be seen later.

****: Final project along with presentation.




\\
\\
Letter grade scale: A(90--100), A--(87--89),  B+(83--86), B(80--82), B--(77--79),\\
C+(73--76), C(70--72), C--(67--69), D+(63--66), D(61--62), D--(60)F(<60)}
\newcommand\HWandLabPolicy{Homework and Project must be submitted according to the designated timeline. LATE SUBMISSION WILL NOT BE ACCEPTED.  Your homework should be neat and with your full name on.}
\newcommand\AttendancePolicy{}
\newcommand\ElectronicsPolicy{\textcolor{red}{Since you opted for a customize electronics policy, you should edit this part. Your policy should address your general stance on recording of class sessions and the circumstances under which recording will be allowed or prohibited. If you generally prohibit recording, yet allow recording of certain classes for some reason, then you should notify all students that those classes will be recorded. If recording is permitted as an ADA accommodation for a student, you obviously should not identify that student(s).}}