Hardware accelerator design, implementation, and security analysis for post-quantum cryptography
Accelerating different fully homomorphic encryption schemes; privacy-preserving machine learning
Novel algorithm-to-architecture co-design and implementation techniques for large-scale digital processing systems
Novel fault attack and detection methodologies for cryptographic circuits and hardware IP protection
New digital design and acceleration techniques for sophisticated aeronautical telemetry systems
Villanova Security and Cryptography (SAC) Lab
University of Pittsburgh, Pittsburgh, PA 01/2013 - 12/2014
Ph.D. in Electrical Engineering
Central South University, Changsha, Hunan, China 09/2007 - 07/2010
M. E. in Control Science and Engineering
Yanshan University, Qinhuangdao, Hebei, China 09/2002 - 07/2006
B. E. in Measurement & Control Technology and Instrumentation
Associate Professor, Department of Electrical and Computer Engineering, Villanova University, August 2024 - Present
Assistant Professor (tenure-track), Department of Electrical and Computer Engineering, Villanova University, August 2018 - August 2024
Assistant Professor (tenure-track), Department of Electrical Engineering, Wright State University, January 2015 - July 2018
Senior Member of IEEE (Member of CAS, Computer, CEDA, Signal, and Blockchain Societies)
Member of ACM
Member of IACR
Technical Committee Member of IEEE CASCOM (Circuits and Systems for Communications)
IEEE Philadelphia Section Engineer of the Year Award, 2024
Art Ryan Award (for advised senior design project), ECE Department, Villanova University, 2023
Tenure Track Faculty Career Development Award, College of Engineering, Villanova University, 2023
AFRL VFRP Award and Extension Award, AFRL, Rome, NY, 2022
IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award for senior design project, 2022
Brian Anderson Memorial Award for senior design project, ECE Department, Villanova University, 2021
IEEE Access Outstanding Associate Editor for the year of 2019
IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Best Paper Award, 2019
Instructor at Villanova University (*: developed by me)
a. ECE-1260 EGR Programming and Applications (designed brand-new slides)
b. ECE-2043/2045 Fundamental Computer Engineering-I Lab
c. ECE-2173 Digital Systems Lab
d. ECE-2431 Embedded Systems-I Lab
e. ECE-2800 Professional Development Seminar
f. ECE-3450 Digital Electronics
g. ECE-3430 Embedded Systems-II* (undergraduate course)
h. ECE-4470 Computer Networks Lab
i. ECE-5170 Introduction to Post-Quantum Computing* (senior-elective)
j. ECE-4970/4971/4971 Senior Design Project I/II
k. ECE-8440 Hardware System Design & Modeling* (graduate course)
l. ECE-8481 Post-Quantum Cryptographic Engeineering* (graduate course)
Instructor at Wright State University
a. EE-2000 Digital Design with HDL
b. EE-2010 Circuit Analysis I
c. EE-4800/6800 Algorithms to VLSI Architectures
d. EE-8000 VLSI Cryptographic Circuits
Pengzhou He (06.2025): Efficient hardware acceleration of post quantum cryptography and fully homomorphic encryption
Samuel Coulon (12.2024): Efficient hardware implementations for critical components of post-quantum cryptography (PQC) and fully-homomorphic encryption (FHE)
Elizabeth Carter (2021): Efficient polynomial multiplication hardware accelerators for lattice-based post-quantum cryptography
Shaik Nazeem Basha (2017): Novel implementation of finite field multipliers over GF(2m) for emerging cryptographic applications
Qiliang Shao (2016): FPGA realization of low register systolic multipliers over GF(2m)
Pingxiuqi Chen (2016): FPGA realization of low register systolic all one polynomial multipliers over GF(2m) and their applications in trinomial multipliers
Total: 21 students
Spring 2016: Pingxiuqi Chen, Kejin Geng, Anuteja Karru, and Apoorva Narayanappa Masineni
Summer 2016: Santosh Teja Sannidhi
Fall 2016: Bhargav Chary Biroju and Akhileswar Kalari
Spring 2017: Mrudula Adira, Gowtham Cheedepudi, Viraat Donthula, Ravi Teja Duggi, Dinesh Gutta, Balakrishna Jannu, Aneesha Kandi, Vijaya Sai Medasani, Pujitha Nimmagadda, Sahithi Ravilla, and Kranthi Kumar Thummalapally
Summer 2017: Leela Krishna Mohan Potluri
Spring 2021: Elizabeth Carter (Undergraduate Senior, Topic: Hardware Implementation of Polynomial Multiplication for Ring-LWE based PQC)
Spring 2024: Samuel Coulon (Graduate, Topic: FPGA Implementation for Falcon PQC)
Current Ph.D. students: Yazheng Tu, Tianyou Bao, and Brendan Funk
Alumni:
Ph.D.: Pengzhou He (now Assistant Professor at Auburn University at Montgomery);
M.S. Students: Samuel Coulon; Elizabeth Carter; Qiliang Shao; Shaik Nazeem Basha; Pingxiuqi Chen;
Others:
Previous B.S. students: Ben Mongirdas and Victor Xu
Previous high-school seniors: Antonio Fiorentino Wong and Christopher Lin
01. Yazheng Tu and Jiafeng Xie, "EMINEM: Efficient FPGA implementation of Mixed-radIx NTT hardware accElerators for NIST post-quantuM cryptography Falcon, Dilithium, and HAWK", ACM Transactions on Reconfigurable Technology and Systems, pp. 1-25, 2025.
02. P. He, T. Bao, and Jiafeng Xie, "High-performance instruction-set hardware accelerator for Ring-Binary-LWE-based lightweight PQC," IEEE Trans. VLSI Systems, vol. 33, no. 5, pp. 1417-1421, 2025.
03. S. Coulon, T. Bao, and Jiafeng Xie, "SCALES: SCALable and area-efficient systolic accelerator for ternary polynomial multiplication," IEEE Computer Architecture Letters, vol. 23, no. 2, pp. 243-246, 2024.
04. T. Bao, P. He, D. Fujimoto, Y. Hayashi, and Jiafeng Xie, "CHIRP: Compact and high-performance FPGA implementation of unified hardware accelerators for Ring-Binary-LWE-based PQC," ACM Trans. Reconfigurable Technology and Systems, vol. 18, no. 2, pp. 1-27, 2024.
05. P. He, Y. Tu, T. Bao, Ç. K. Koç, and Jiafeng Xie, "HSPA: High-throughput sparse polynomial multiplication accelerators for code-based post-quantum cryptography," ACM Trans. Embedded Computing Systems, vol. 24, no. 1, pp. 1-24, 2024.
06. Y. Tu, S. Bai, J. Xiong and J. Xie, "SCOPE: Schoolbook-originated novel polynomial multiplication accelerators for NTRU-Based PQC," IEEE Trans. VLSI Systems, vol. 33, no. 2, pp. 408-420, 2024.
07. Y. Tu, T. Bao, P. He, L. Sousa and J. Xie, "LTE: Lightweight and timing-efficient unequal-sized polynomial multiplication accelerators," IEEE Trans. Circuits and Systems II, vol. 72, no. 1, pp. 253-257, 2024.
08. Y. Tu, P. He, C.-H. Chang, and Jiafeng Xie, "LTE: Lightweight and time-efficient hardware encoder for post-quantum scheme HQC," IEEE Computer Architecture Letters, vol. 23, no. 2, pp. 187-190, 2024.
09. S. Coulon, T. Bao, and Jiafeng Xie, "FELIX: FPGA-based Scalable and Lightweight Accelerator for Large Integer Extended GCD," IEEE Trans. VLSI Systems, vol. 32, no. 9, pp. 1684-1695, 2024.
10. Jiafeng Xie, W. Zhao, H. Lee, D. B. Roy, and X. Zhang, "Hardware circuits and systems design for post-quantum cryptography – A tutorial brief," IEEE Trans. Circuits and Systems II, vol. 71, no. 3, pp. 1670-1676, 2024 (popular paper in IEEE Xplore).
11. P. He, S. C. Oliva Madrigal, Ç. K. Koç, T. Bao, and Jiafeng Xie, "CASA: A compact and scalable accelerator for approximate homomorphic encryption," IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), vol. 2024, no. 2, pp. 1-30, 2024.
[First 11 of 48 total papers - full list available in CV]
01. S. Coulon, J. Xiong, and Jiafeng Xie, "LEAF: Lightweight and Efficient Hardware Accelerator for Signature Verification of FALCON," 2025 International Conference on Computer-Aided Design (ICCAD), pp. 1-9, 2025.
02. S. Coulon, T. Bao, and Jiafeng Xie, "Efficient post-quantum cryptographic hardware for healthcare applications," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2025.
03. T. Bao, P. He, and Jiafeng Xie, "Invited paper: Enhancing privacy-preserving computing with optimized CKKS encryption: A hardware acceleration approach," 2024 International Conference on Computer-Aided Design (ICCAD), Article 11, pp. 1-9, 2024.
04. P. He, B. Mongirdas, Ç. Koç and Jiafeng Xie, "LAMP: Efficient implementation of lightweight accelerator for polynomial multiplication, from Falcon to RBLWE-ENC," ACM GLSVLSI, pp. 210-215, 2024.
05. P. He, T. Bao, Ç. Koç, Jiafeng Xie, "HELP: Highly efficient and low-latency hardware accelerator for integer polynomial multiplication," IEEE Computer Society Annual Symposium on VLSI, pp. 355-360, 2024.
06. Jiafeng Xie, P. He, S. C.O. Madrigal and Ç. Koç, "SMALL: Scalable matrix originated large integer polynomial multiplication accelerator for lattice-based post-quantum cryptography," International Workshop on the Arithmetic of Finite Fields (WAIFI), pp. 274-292, 2024.
07. S. Coulon, P. He, T. Bao, Jiafeng Xie, "Efficient hardware RNS decomposition for post-quantum signature scheme FALCON," 57th Asilomar Conference on Signals, Systems, and Computers, pp. 1-8, 2023.
08. P. He*, T. Bao*, Y. Tu, and Jiafeng Xie, "Efficient implementation of Ring-Binary-LWE-based lightweight PQC accelerator on the FPGA platform," IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2023), pp. 114-120, 2023 (*: equal contribution).
09. P. He, Y. Tu, and Jiafeng Xie, "LOCS: Low-latency and constant-timing implementation of fixed-weight sampler for HQC," IEEE International Symposium on Circuits and Systems-2023 (ISCAS'23), pp. 1-5, 2023.
10. P. He and J. Xie, "Novel Implementation of High-performance polynomial multiplication for unified KEM Saber based on TMVP design strategy," International Symposium on Quality Electronic Design (ISQED), pp. 1-8, 2023.
[First 10 of 33 total conference papers - full list available in CV]
Design and Implementation of Compact and Scalable Hardware Accelerator for Approximate Homomorphic Encryption. University of Delaware, DE, 10/9/2024
Hardware Acceleration for Post-Quantum Cryptography: Algorithmic Derivation, and Architectural Innovation, Temple University, Philadelphia, PA, 9/27/2023
Hardware Acceleration for Post-Quantum Cryptography: Algorithmic Derivation, and Architectural Innovation, Florida Atlantic University, Boca Raton, FL, 12/14/2022
Hardware acceleration for post-quantum cryptography: recent advance, algorithmic derivation, and architectural innovation, AFRL, Rome, NY, 7/7/2022
Obfuscating systolic-array-based circuits via novel algorithm-to-architecture mapping techniques, Villanova University, 02/15/2018
FPGA implementation of low-complexity systolic Karatsuba multiplier over GF(2m) based on NIST polynomials, Department of Automation, Central South University, 03/17/2017
How to prepare yourself for future career (career center invited seminar), Wright State University, 09/04/2016
Novel single and hybrid finite field multipliers over GF(2m) for emerging cryptographic systems, Wright State University, 07/20/2016
Novel cryptosystem for secure data transmission related to control systems, School of Information Science and Engineering, Central South University, 05/27/2016
Novel finite field multipliers over GF(2m) for emerging cryptographic systems, Department of Electrical Engineering, Wright State University, 10/31/2014
Novel finite field multipliers over GF(2m) for emerging cryptographic systems, Department of Electrical Engineering, University of Michigan, Dearborn, 02/11/2014
Senior Associate Editor:
IEEE Trans. Circuits and Systems-II (2024 – )
Associate Editor:
IEEE Trans. Signal Processing (2025 – 2027)
IEEE Trans. VLSI Systems (2023 – 2024)
IEEE Access (2017 – 2024)
Microelectronics Journal (2016 – 2022)
IEEE Trans. Circuits and Systems-II (2020)
National Science Foundation SaTC and SCC
Proceedings of the IEEE
IEEE Trans. Industrial Electronics
ACM Journal on Emerging Technologies in Computing Systems
IEEE Trans. Emerging Topics in Computing
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Circuits and Systems-I
IEEE Trans. Circuits and Systems-II
IEEE Trans. VLSI Systems
IEEE Access
Microelectronics Journal
Microprocessors and Microsystems
Integration, the VLSI
IET Signal Processing
Multidimensional Systems and Signal Processing
Journal of Signal Processing Systems
IET Circuits, Devices & Systems
AEU International Journal of Electronics and Communications
IEEE Transactions on Emerging Topics in Computing
ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Embedded Computing Systems
ACM Journal on Emerging Technologies in Computing Systems
Hawaii International Conference on System Sciences
IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2019, 2020, 2021, 2022
IEEE International Conference on Computer Design (ICCD) 2018, 2019, 2022
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2019, 2020, 2021
Asia and South Pacific Design Automation Conference (ASP-DAC) 2020
IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2020, 2021, 2022
Design Automation Conference (DAC) 2020, 2021, 2022
GLSVLSI 2021, 2022
The International Conference on Hardware/Software Codesign and System
Synthesis (CODES+ISSS) 2021, 2022
International Conference On Computer Aided Design (ICCAD) 2021, 2022
Top Picks in Hardware and Embedded Security 2021
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) 2022
IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP 2022)
International Conference on Field Programmable Technology (FPT) 2022
IEEE International Conference on Computer Design (ICCD) 2018, 2019
International Symposium on Hardware Oriented Security and Trust (HOST) 2020
Top Picks in Hardware and Embedded Security 2021
Design Automation Conference (DAC) 2021
IEEE International Symposium on Circuits and Systems (ISCAS) 2022, 2023, 2025
ARITH 2022
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2022
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2022
International Conference on Field-Programmable Technology (FPT) 2023
International Conference on Computer-Aided Design (ICCAD) 2025