This position is fully funded. Interested candidates please send your CV to Prof. Xie at jiafeng.xie@villanova.edu.
Research area in hardware acceleration and side-channel analysis for post-quantum cryptography.
New source code related to hardware implementation of HQC have been released. See Resource Section for details.
Prof. Jiafeng Xie has been promoted to Associate Professor with tenure effective August 2024!
Senior design project received 2022 IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award and Brian Anderson Memorial Award from ECE Department of Villanova University! Congratulations again, Benjamin, Ali, Marion, David, Andrew! Source code see Resources.
Prof. Xie received the prestigious IEEE Philadelphia Section Engineer of the Year Award for 2024!
Brendan Funk joined the lab in Fall 2024!
The SAC Lab has signed Educational Partnership Agreement (EPA) with AFRL, Rome, NY.
The Security and Cryptography (SAC) Lab is an academic research lab at Villanova University, led by Prof. Jiafeng (Harvest) Xie. The SAC lab conducts research in a variety of deeply technical topics in Cryptographic Engineering, Fault Attacks and Detection, Hardware Security, VLSI Neural Network Systems and Novel Computer Arithmetic.
Hardware accelerator design, implementation, and security analysis for post-quantum cryptography.
Accelerating various fully homomorphic encryption schemes and enabling privacy-preserving machine learning and data analytics.
Novel fault attack and detection methodologies for cryptographic circuits and hardware IP protection.
Novel algorithm-to-architecture co-design and implementation techniques for large-scale digital processing systems.
New digital design and acceleration techniques for sophisticated aeronautical telemetry systems.
2025
EMINEM: Efficient FPGA implementation of Mixed-radIx NTT hardware accElerators for NIST post-quantuM cryptography Falcon, Dilithium, and HAWK
Y. Tu and Jiafeng Xie ACM Transactions on Reconfigurable Technology and Systems, pp. 1-25, 2025.
High-performance instruction-set hardware accelerator for Ring-Binary-LWE-based lightweight PQC
P. He, T. Bao, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 33, no. 5, pp. 1417-1421, 2025.
LEAF: Lightweight and Efficient Hardware Accelerator for Signature Verification of FALCON
S. Coulon, J. Xiong, and Jiafeng Xie 2025 International Conference on Computer-Aided Design (ICCAD), pp. 1-9, 2025.
Efficient post-quantum cryptographic hardware for healthcare applications
S. Coulon, T. Bao, and Jiafeng Xie 2025 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2025.
2024
SCALES: SCALable and area-efficient systolic accelerator for ternary polynomial multiplication
S. Coulon, T. Bao, and Jiafeng Xie IEEE Computer Architecture Letters, vol. 23, no. 2, pp. 243-246, 2024.
CHIRP: Compact and high-performance FPGA implementation of unified hardware accelerators for Ring-Binary-LWE-based PQC
T. Bao, P. He, D. Fujimoto, Y. Hayashi, and Jiafeng Xie ACM Trans. Reconfigurable Technology and Systems, vol. 18, no. 2, pp. 1-27, 2024.
HSPA: High-throughput sparse polynomial multiplication accelerators for code-based post-quantum cryptography
P. He, Y. Tu, T. Bao, Ç. K. Koç, and Jiafeng Xie ACM Trans. Embedded Computing Systems, vol. 24, no. 1, pp. 1-24, 2024.
SCOPE: Schoolbook-originated novel polynomial multiplication accelerators for NTRU-Based PQC
Y. Tu, S. Bai, J. Xiong and J. Xie IEEE Trans VLSI Systems, vol. 33, no. 2, pp. 408-420, 2024.
LTE: Lightweight and timing-efficient unequal-sized polynomial multiplication accelerators
Y. Tu, T. Bao, P. He, L. Sousa and J. Xie IEEE Trans. Circuits and Systems II, vol. 72, no. 1, pp. 253-257, 2024.
LTE: Lightweight and time-efficient hardware encoder for post-quantum scheme HQC
Y. Tu, P. He, C.-H. Chang, and Jiafeng Xie IEEE Computer Architecture Letters, vol. 23, no. 2, pp. 187-190, 2024.
FELIX: FPGA-based Scalable and Lightweight Accelerator for Large Integer Extended GCD
S. Coulon, T. Bao, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 32, no. 9, pp. 1684-1695, 2024.
Hardware circuits and systems design for post-quantum cryptography – A tutorial brief
Jiafeng Xie, W. Zhao, H. Lee, D. B. Roy, and X. Zhang IEEE Trans. Circuits and Systems II, vol. 71, no. 3, pp. 1670-1676, 2024 (popular paper in IEEE Xplore).
CASA: A compact and scalable accelerator for approximate homomorphic encryption
P. He, S. C. Oliva Madrigal, Ç. K. Koç, T. Bao, and Jiafeng Xie IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), vol. 2024, no. 2, pp. 1-30, 2024.
TINA: TMVP initiated novel accelerator for lightweight Ring-LWE-based PQC
T. Bao, P. He, S. Bai, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 32, no. 5, pp. 870-882, 2024.
AEKA: FPGA implementation of area-efficient Karatsuba accelerator for Ring-Binary-LWE-based lightweight PQC
T. Bao, P. He, Jiafeng Xie, and H S. Jacinto ACM Trans. Reconfigurable Technology and Systems, vol. 17, no. 2, pp. 1-23, 2024 (FPT'23-Journal Track).
2023
KINA: Karatsuba initiated novel accelerator for Ring-Binary-LWE (RBLWE)-based post-quantum cryptography
P. He, Y. Tu, Jiafeng Xie, and H S. Jacinto IEEE Trans. VLSI Systems, vol. 31, no. 10, pp. 1551-1564, 2023.
Hardware-implemented lightweight accelerator for large integer polynomial multiplication
P. He, Y. Tu, Ç. K. Koç, and Jiafeng Xie IEEE Computer Architecture Letters, vol. 22, no. 1, pp. 57-60, 2023.
LEAP: Lightweight and efficient accelerator for sparse polynomial multiplication of HQC
Y. Tu, P. He, Ç.K. Koç, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 31, no. 6, pp. 892-896, 2023.
COPMA: Compact and optimized polynomial multiplier accelerator for high-performance implementation of LWR-based PQC
P. He, Y. Tu, T. Bao, L. Sousa, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 31, no. 4, pp. 596-600, 2023.
2022
FPGA implementation of compact hardware accelerators for Ring-Binary-LWE based post-quantum cryptography
P. He, T. Bao, Jiafeng Xie, and M. Amin ACM Trans. Reconfigurable Technology and Systems, vol. 15, no. 3, pp. 1-23, 2022 (FPT'22-Journal Track).
AFIA: ATPG-guided fault injection attack on secure logic locking
Y. Zhong, A. Jain, M.T. Rahman, N. Adadi, Jiafeng Xie, and U. Guin Journal of Electronic Testing: Theory and Applications (JETTA), vol. 38, pp. 527–546, 2022.
Efficient hardware arithmetic for inverted Binary Ring-LWE based post-quantum cryptography
J. Imana*, P. He*, T. Bao, Y. Tu, and Jiafeng Xie IEEE Trans. Circuits and Systems-I, vol. 69, no. 8, pp. 3297-3307, 2022 (*: equal contribution).
Lightweight hardware implementation of binary Ring-LWE PQC accelerator
B. J. Lucas, A. Alwan, M. Murzello, Y. Tu, P. He, A. J. Schwartz, D. Guevara, U. Guin, K. Juretus, and Jiafeng Xie IEEE Computer Architecture Letters, vol. 21, no. 1, pp. 17-20, 2022 (popular paper in IEEE Xplore).
Efficient hardware implementation of large field-size Elliptic Curve Cryptographic processor
C. -Y. Lee, M. Zeghid, A. Sghaier, H. Y. Ahmed and Jiafeng Xie IEEE Access, 10: 7926-7936, 2022.
Certificateless signature schemes in industrial Internet of Things: A comparative survey
S. Hussain, S. Ullah, I. Ali, Jiafeng Xie, and V. Inukollu Computer Communications, vol. 181, pp. 116-131, 2022.
Efficient hardware implementation of finite field arithmetic AB + C for binary Ring-LWE based post-quantum cryptography
Jiafeng Xie, P. He, X. Wang, and J. Imana IEEE Trans. Emerging Topics in Computing, vol. 10, no. 2, pp. 1222-1228, 2022.
2021
Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary Ring-LWE post-quantum cryptography
P. He, U. Guin, and Jiafeng Xie IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 11, no. 2, pp. 383-394, 2021.
Ultra low-complexity implementation of binary Ring-LWE based post-quantum cryptography on FPGA platform
Jiafeng Xie, P. He, and T. Bao ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2022, (poster).
CROP: FPGA implementation of high-performance polynomial multiplication in Saber KEM based on novel cyclic-row oriented processing strategy
Jiafeng Xie, P. He, and C.Y. Lee IEEE International Conference on Computer Design (ICCD), pp. 130-137, 2021.
Compact coprocessor for KEM Saber: novel scalable matrix originated processing
P. He, C. Lee, and Jiafeng Xie NIST Third PQC Standardization Conference, pp. 1-16, 2021 (presentation).
Efficient implementation of finite field arithmetic for binary Ring-LWE post-quantum cryptography through a novel lookup-table-like method
Jiafeng Xie, P. He, and W. Wen Design Automation Conference (DAC), pp. 1279-1284, 2021.
Previous
Special Session: The recent advance of hardware implementation of post-quantum cryptography
Jiafeng Xie, K. Basu, Kris, M. Gaj, and U. Guin IEEE VLSI Testing Symposium (VTS), pp. 1-10, 2020 (invited).
Efficient subquadratic space complexity digit-serial multipliers over GF(2m) based on bivariate polynomial basis representation
C. Lee and Jiafeng Xie Asia and South Pacific Design Automation Conference (ASPDAC), pp. 1-6, 2020.
Novel bit-parallel and digit-serial systolic finite field multipliers over GF(2m) based on reordered normal basis
Jiafeng Xie, C. Lee, P. Meher, and Z.-H. Mao IEEE Trans. VLSI Systems, vol. 27, no. 9, pp. 2119-2130, 2019.
Novel systolization of subquadratic space complexity multipliers based on Toeplitz matrix-vector product approach
J. Pan, C. Lee, A. Sghaier, M. Zeghid, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 27, no. 7, pp. 1614-1622, 2019.
Digit-serial versatile multiplier based on a novel block recombination of the modified overlap-free Karatsuba algorithm
C. Lee and Jiafeng Xie IEEE Trans. Circuits and Systems-I, vol. 66, no. 1, pp. 203-214, 2019.
Efficient scalable three operand oultiplier over GF(2m) based on novel decomposition strategy
C. Lee and Jiafeng Xie IEEE International Conference on Computer Design (ICCD), pp. 1-9, 2019.
High capability and low-complexity: Novel fault detection scheme for finite field multipliers over GF(2m) based on MSPB
C. Lee and Jiafeng Xie IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 21-30, 2019 (Best Paper Award).
Low-complexity systolic multiplier for GF(2m) using Toeplitz Matrix-Vector Product method
Jiafeng Xie, C. Lee, and P. K. Meher IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
LSM: Novel low-complexity unified systolic multiplier over binary extension field
Jiafeng Xie and C. Lee ACM Great Lakes Symposium on VLSI (GLVLSI), 2019.
Embracing systolic: super systolization of large-scale circulant matrix-vector multiplication on FPGA with subquadratic space complexity
Jiafeng Xie and C. Lee ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
Low register-complexity systolic digit-serial multiplier over GF(2m) based on trinomials
Jiafeng Xie, P. Meher, X. Zhou, and J. Zhang IEEE Trans. Multiscale Computing Systems, vol. 4, no. 4, pp. 773-783, 2018.
Novel hybrid-size digit-serial systolic multiplier over GF(2m)
Z. Hu and Jiafeng Xie Symmetry, vol. 10, no. 11, pp. 1-11, 2018.
Efficient implementation of Karatsuba algorithm based three-operand multiplication over binary extension field
C. Lee, C. Fan, Jiafeng Xie, and S. Yuan IEEE Access, 6: 38234-38242, 2018.
Low complexity implementation of unified systolic multipliers for NIST pentanomials and trinomials over GF(2m)
Q. Shao, Z. Hu, S. Basha, Z. Zhang, Z. Wu, C.Y. Lee, and Jiafeng Xie IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 65, no. 8, pp. 2455-2465, 2018.
Reliable inversion in GF(28) with redundant arithmetic for secure error detection of cryptographic architectures
M. Kermani, A. Jalali, R. Azarderakhsh, Jiafeng Xie, and K.K. R. Choo IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, vol. 37, no. 3, pp. 696-704, 2018.
Low area-delay complexity digit-level parallel-in serial-out multiplier over GF(2m) based on overlap-free Karatsuba algorithm
C. Lee and Jiafeng Xie IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2018.
Efficient FPGA implementation of low-complexity systolic Karatsuba multiplier over GF(2m) based on NIST polynomials
Jiafeng Xie, P.K. Meher, M. Sun, Y. Li, B. Zeng, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 64, no. 7, pp, 1815-1825, 2017.
Low-complexity digit-level systolic Gaussian normal basis multiplier
Q. Shao, Z. Hu, S. Chen, P. Chen, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 25, no. 10, pp. 2817-2827, 2017.
FPGA realization of low register systolic all-one-polynomial multipliers over GF(2m) and their applications in trinomial multipliers
P. Chen, N. Basha, M. Kermani, R. Azarderakhsh, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 25, no. 9, pp. 725-734, 2017.
Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits
Jiafeng Xie and X. Zhou IEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2017.
DNA-cryptography-based obfuscated systolic finite field multiplier for secure cryptosystem in smart grid
S. Chen, P. Chen, Q. Shao, S. Basha, and Jiafeng Xie Asia Conference on Power and Electrical Engineering (ACPEE), pp. 1-6, 2017.
Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes
M. Kermani, R. Azarderakhsh, and Jiafeng XieIEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2016.
Low-latency high-throughput systolic multipliers over GF(2m) for NIST recommended pentanomials
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 3, pp. 881-890, 2015.
High-throughput digit-level systolic multiplier over GF(2m) based on irreducible trinomials
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 62, no. 5, pp. 481-485, 2015.
High-throughput finite field multipliers using redundant basis for FPGA and ASIC implementations
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 1, pp. 110-119, 2015.
Hardware-efficient realization of prime-length DCT based on distributed arithmetic
Jiafeng Xie, J. He, and P.K. Meher IEEE Trans. Computers, vol. 62, no. 6, pp. 1170-1178, 2013.
Low-complexity multiplier for GF(2m) based on all one polynomials
Jiafeng Xie, P.K. Meher, and J. He IEEE Trans. VLSI Systems, vol. 21, no. 1, pp. 168-172, 2013.
Low latency systolic Montgomery multiplier for finite field GF(2m) based on pentanomials
Jiafeng Xie, J. He, and P.K. Meher IEEE Trans. VLSI Systems, vol. 21, no. 2, pp. 385-389, 2013.
FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures
Jiafeng Xie, J. He, and G. Tan Microelectronics Journal (Elsevier), vol. 41, no. 6, pp. 365-370, 2010.
...
IEEE Philadelphia Section Engineer of the Year Award, 2024
IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award, 2022
Brian Anderson Memorial Award from ECE Department, Villanova University 2022
IEEE Access Outstanding Associate Editor, 2019
IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Best Paper Award, 2019
You are free to use the resources shared below if used for non-profit purposes or open source projects. Please quote resources in the project from Villanova University Security & Cryptography Lab. :)
The SAC Lab is not responsible for the correctness of the source code.
Github Link: https://github.com/harvestsp
Source code and supplementary materials for HQC sparse polynomial multiplication implementations.
Reference: P. He, Y. Tu, T. Bao, Ç. K. Koç, and J. Xie, “HSPA: High-throughput sparse polynomial multiplication accelerators for code-based post-quantum cryptography,” ACM Trans. Embedded Computing Systems, vol. 24, no. 1, pp. 1–24, 2024.
GitHub: https://github.com/nobsessive/HSPA
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Source code for the two architectures presented in the paper of "Efficient hardware arithmetic for inverted Binary Ring-LWE based post-quantum cryptography"
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Source code for the low complexity and high speed architectures presented in the paper of "Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator"
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Source code for the polynomial multiplication (Fig. 3) presented in the paper of "Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary Ring-LWE post-quantum cryptography"
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