TCAS-I paper got accepted! Source code see Resources.
Senior design project received 2022 IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award and Brian Anderson Memorial Award from ECE Department of Villanova University! Congratulations again, Benjamin, Ali, Marion, David, Andrew! Source code see Resources.
Senior design project is included in a paper accepted in IEEE Computer Architecture Letters. Congratulations, Benjamin, Ali, Marion, Yazheng, David, and Andrew! Source code see Resources.
We have redesigned the website of the laboratory and added a lot of interesting content!
Yazheng Tu joined our lab in Summer 2021, and Tianyou Bao joined the lab in Fall 2021!
The SAC Lab has signed Educational Partnership Agreement (EPA) with AFRL, Rome, NY.
The Security and Cryptography (SAC) Lab is an academic research lab at Villanova University, led by Prof. Jiafeng (Harvest) Xie. The SAC lab conducts research in a variety of deeply technical topics in Cryptographic Engineering, Fault Attacks and Detection, Hardware Security, VLSI Neural Network Systems and Novel Computer Arithmetic.
Efficient design and implementation of post-quantum cryptography on different application platforms as well as related implementation technique development.
Develop novel fault attack strategies toward different cryptosystems and related countermeasures and mitigation techniques.
Hardware Intellectual Property protection strategy development as well as related security issues.
Develop novel computer arithmetic for emerging computational-intensive systems and Design efficient VLSI architecture for neural network systems.
2022
J. Imãna*, P. He*, T. Bao, Y. Tu, and Jiafeng Xie IEEE Transactions on Circuits and Systems-I, 2022 (accepted, *: equal contribution).
B. J. Lucas, A. Alwan, M. Murzello, Y. Tu, P. He, A. J. Schwartz, D. Guevara, U. Guin, K. Juretus, and Jiafeng Xie IEEE Computer Architecture Letters, 2022 (accepted).
C. -Y. Lee, M. Zeghid, A. Sghaier, H. Y. Ahmed and Jiafeng Xie IEEE Access, pp. 1-11, 2022 (accepted).
T. Bao, P. He, and Jiafeng Xie IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 1-4, 2022 (accepted).
Y. Tu, P. He, C. Lee, D. Chasaki, and Jiafeng Xie IEEE International Symposium on Circuits and Systems-2022 (ISCAS’22), pp. 1-5, 2022 (accepted).
2021
Jiafeng Xie, P. He, and T. Bao ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2022, (poster).
S. Hussain, S. Ullah, I. Ali, Jiafeng Xie, and V. Inukollu Computer Communications, pp. 1-16, 2021 (accepted).
Y. Tu, P. He, U. Guin, and Jiafeng Xie GOMACTech, pp. 1-6, 2022 (accepted for presentation).
P. He, C. Lee, and Jiafeng Xie NIST Third PQC Standardization Conference, pp. 1-16, 2021 (presentation).
Jiafeng Xie, P. He, and C.Y. Lee IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2021.
Jiafeng Xie, P. He, X. Wang, and J. Imana IEEE Trans. Emerging Topics in Computing, pp. 1-6, 2021.
P. He, U. Guin, and Jiafeng Xie IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp. 1-13, 2021.
Jiafeng Xie, P. He, and W. Wen Design Automation Conference (DAC), pp. 1-6, 2021
Previous
Jiafeng Xie, K. Basu, Kris, M. Gaj, and U. Guin IEEE VLSI Testing Symposium (VTS), pp. 1-10, 2020 (invited).
C. Lee and Jiafeng Xie Asia and South Pacific Design Automation Conference (ASPDAC), pp. 1-6, 2020.
Jiafeng Xie, C. Lee, P. Meher, and Z.-H. Mao IEEE Trans. VLSI Systems, vol. 27, no. 9, pp. 2119-2130, 2019.
J. Pan, C. Lee, A. Sghaier, M. Zeghid, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 27, no. 7, pp. 1614-1622, 2019.
C. Lee and Jiafeng Xie IEEE Trans. Circuits and Systems-I, vol. 66, no. 1, pp. 203-214, 2019.
C. Lee and Jiafeng Xie IEEE International Conference on Computer Design (ICCD), pp. 1-9, 2019.
C. Lee and Jiafeng Xie IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 21-30, 2019 (Best Paper Award).
Jiafeng Xie, C. Lee, and P. K. Meher IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
Jiafeng Xie and C. Lee ACM Great Lakes Symposium on VLSI (GLVLSI), 2019.
Jiafeng Xie and C. Lee ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
Jiafeng Xie, P. Meher, X. Zhou, and J. Zhang IEEE Trans. Multiscale Computing Systems, vol. 4, no. 4, pp. 773-783, 2018.
Z. Hu and Jiafeng Xie Symmetry, vol. 10, no. 11, pp. 1-11, 2018.
C. Lee, C. Fan, Jiafeng Xie, and S. Yuan IEEE Access, 6: 38234-38242, 2018.
Q. Shao, Z. Hu, S. Basha, Z. Zhang, Z. Wu, C.Y. Lee, and Jiafeng Xie IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 65, no. 8, pp. 2455-2465, 2018.
M. Kermani, A. Jalali, R. Azarderakhsh, Jiafeng Xie, and K.K. R. Choo IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, vol. 37, no. 3, pp. 696-704, 2018.
C. Lee and Jiafeng Xie IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2018.
Jiafeng Xie, P.K. Meher, M. Sun, Y. Li, B. Zeng, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 64, no. 7, pp, 1815-1825, 2017.
Q. Shao, Z. Hu, S. Chen, P. Chen, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 25, no. 10, pp. 2817-2827, 2017.
P. Chen, N. Basha, M. Kermani, R. Azarderakhsh, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 25, no. 9, pp. 725-734, 2017.
Jiafeng Xie and X. Zhou IEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2017.
S. Chen, P. Chen, Q. Shao, S. Basha, and Jiafeng Xie Asia Conference on Power and Electrical Engineering (ACPEE), pp. 1-6, 2017.
M. Kermani, R. Azarderakhsh, and Jiafeng XieIEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2016.
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 3, pp. 881-890, 2015.
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 62, no. 5, pp. 481-485, 2015.
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 1, pp. 110-119, 2015.
Jiafeng Xie, J. He, and P.K. Meher IEEE Trans. Computers, vol. 62, no. 6, pp. 1170-1178, 2013.
Jiafeng Xie, P.K. Meher, and J. He IEEE Trans. VLSI Systems, vol. 21, no. 1, pp. 168-172, 2013.
Jiafeng Xie, J. He, and P.K. Meher IEEE Trans. VLSI Systems, vol. 21, no. 2, pp. 385-389, 2013.
Jiafeng Xie, J. He, and G. Tan Microelectronics Journal (Elsevier), vol. 41, no. 6, pp. 365-370, 2010.
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IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award, 2022
Brian Anderson Memorial Award from ECE Department, Villanova University 2022
IEEE Access Outstanding Associate Editor, 2019
IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Best Paper Award, 2019
You are free to use the resources shared below if used for non-profit purposes or open source projects. Please quote resources in the project from Villanova University Security & Cryptography Lab. :)
The SAC Lab is not responsible for the correctness of the source code.
Github Link: https://github.com/harvestsp
Source code for the polynomial multiplication (Fig. 3) presented in the paper of "Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary Ring-LWE post-quantum cryptography"
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Source code for the low complexity and high speed architectures presented in the paper of "Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator"
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Source code for the two architectures presented in the paper of "Efficient hardware arithmetic for inverted Binary Ring-LWE based post-quantum cryptography"
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