Welcome to Villanova Security and Cryptography (SAC) Lab

Announcement

The SAC Lab welcomes talented students to participate in research activities.
If you are interested to join our group, please contact Prof. Xie at jiafeng.xie@villanova.edu

News

TCAS-I paper got accepted! Source code see Resources.

Senior design project received 2022 IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award and Brian Anderson Memorial Award from ECE Department of Villanova University! Congratulations again, Benjamin, Ali, Marion, David, Andrew! Source code see Resources.

Senior design project is included in a paper accepted in IEEE Computer Architecture Letters. Congratulations, Benjamin, Ali, Marion, Yazheng, David, and Andrew! Source code see Resources.

We have redesigned the website of the laboratory and added a lot of interesting content!

Yazheng Tu joined our lab in Summer 2021, and Tianyou Bao joined the lab in Fall 2021!

The SAC Lab has signed Educational Partnership Agreement (EPA) with AFRL, Rome, NY.

About Us

The Security and Cryptography (SAC) Lab is an academic research lab at Villanova University, led by Prof. Jiafeng (Harvest) Xie. The SAC lab conducts research in a variety of deeply technical topics in Cryptographic Engineering, Fault Attacks and Detection, Hardware Security, VLSI Neural Network Systems and Novel Computer Arithmetic.

3

Projects

38

Papers

Research Areas We Focus on

Post-Quantum Cryptography

Efficient design and implementation of post-quantum cryptography on different application platforms as well as related implementation technique development.

Fault Attack and Detection

Develop novel fault attack strategies toward different cryptosystems and related countermeasures and mitigation techniques.

Hardware Security

Hardware Intellectual Property protection strategy development as well as related security issues.

Computer Arithmetic and VLSI Neural Network Systems

Develop novel computer arithmetic for emerging computational-intensive systems and Design efficient VLSI architecture for neural network systems.

Supported by

NSF
NIST

Publication

2022

Efficient hardware arithmetic for inverted Binary Ring-LWE based post-quantum cryptography
J. Imãna*, P. He*, T. Bao, Y. Tu, and Jiafeng Xie IEEE Transactions on Circuits and Systems-I, 2022 (accepted, *: equal contribution).

Lightweight hardware implementation of binary Ring-LWE PQC accelerator
B. J. Lucas, A. Alwan, M. Murzello, Y. Tu, P. He, A. J. Schwartz, D. Guevara, U. Guin, K. Juretus, and Jiafeng Xie IEEE Computer Architecture Letters, 2022 (accepted).

Efficient hardware implementation of large field-size Elliptic Curve cryptographic processor
C. -Y. Lee, M. Zeghid, A. Sghaier, H. Y. Ahmed and Jiafeng Xie IEEE Access, pp. 1-11, 2022 (accepted).

Systolic acceleration of polynomial multiplication for KEM Saber and binary Ring-LWE post-quantum cryptography
T. Bao, P. He, and Jiafeng Xie IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 1-4, 2022 (accepted).

Hardware implementation of high-performance polynomial multiplication for KEM Saber
Y. Tu, P. He, C. Lee, D. Chasaki, and Jiafeng Xie IEEE International Symposium on Circuits and Systems-2022 (ISCAS’22), pp. 1-5, 2022 (accepted).

2021

Ultra low-complexity implementation of binary Ring-LWE based post-quantum cryptography on FPGA platform
Jiafeng Xie, P. He, and T. Bao ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2022, (poster).

Certificateless signature schemes in industrial Internet of Things: A comparative survey
S. Hussain, S. Ullah, I. Ali, Jiafeng Xie, and V. Inukollu Computer Communications, pp. 1-16, 2021 (accepted).

Low-complexity implementation of lightweight Ring-LWE based post-quantum cryptography
Y. Tu, P. He, U. Guin, and Jiafeng Xie GOMACTech, pp. 1-6, 2022 (accepted for presentation).

Compact coprocessor for KEM Saber: novel scalable matrix originated processing
P. He, C. Lee, and Jiafeng Xie NIST Third PQC Standardization Conference, pp. 1-16, 2021 (presentation).

CROP: FPGA implementation of high-performance polynomial multiplication in Saber KEM based on novel cyclic-row oriented processing strategy
Jiafeng Xie, P. He, and C.Y. Lee IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2021.

Efficient hardware implementation of finite field arithmetic AB + C for binary Ring-LWE based post-quantum cryptography
Jiafeng Xie, P. He, X. Wang, and J. Imana IEEE Trans. Emerging Topics in Computing, pp. 1-6, 2021.

Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary Ring-LWE post-quantum cryptography
P. He, U. Guin, and Jiafeng Xie IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp. 1-13, 2021.

Efficient implementation of finite field arithmetic for binary Ring-LWE post-quantum cryptography through a novel lookup-table-like method
Jiafeng Xie, P. He, and W. Wen Design Automation Conference (DAC), pp. 1-6, 2021


Previous

Special Session: The recent advance of hardware implementation of post-quantum cryptography
Jiafeng Xie, K. Basu, Kris, M. Gaj, and U. Guin IEEE VLSI Testing Symposium (VTS), pp. 1-10, 2020 (invited).

Efficient subquadratic space complexity digit-serial multipliers over GF(2m) based on bivariate polynomial basis representation
C. Lee and Jiafeng Xie Asia and South Pacific Design Automation Conference (ASPDAC), pp. 1-6, 2020.

Novel bit-parallel and digit-serial systolic finite field multipliers over GF(2m) based on reordered normal basis
Jiafeng Xie, C. Lee, P. Meher, and Z.-H. Mao IEEE Trans. VLSI Systems, vol. 27, no. 9, pp. 2119-2130, 2019.

Novel systolization of subquadratic space complexity multipliers based on Toeplitz matrix-vector product approach
J. Pan, C. Lee, A. Sghaier, M. Zeghid, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 27, no. 7, pp. 1614-1622, 2019.

Digit-serial versatile multiplier based on a novel block recombination of the modified overlap-free Karatsuba algorithm
C. Lee and Jiafeng Xie IEEE Trans. Circuits and Systems-I, vol. 66, no. 1, pp. 203-214, 2019.

Efficient scalable three operand oultiplier over GF(2m) based on novel decomposition strategy
C. Lee and Jiafeng Xie IEEE International Conference on Computer Design (ICCD), pp. 1-9, 2019.

High capability and low-complexity: Novel fault detection scheme for finite field multipliers over GF(2m) based on MSPB
C. Lee and Jiafeng Xie IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 21-30, 2019 (Best Paper Award).

Low-complexity systolic multiplier for GF(2m) using Toeplitz Matrix-Vector Product method
Jiafeng Xie, C. Lee, and P. K. Meher IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

LSM: Novel low-complexity unified systolic multiplier over binary extension field
Jiafeng Xie and C. Lee ACM Great Lakes Symposium on VLSI (GLVLSI), 2019.

Embracing systolic: super systolization of large-scale circulant matrix-vector multiplication on FPGA with subquadratic space complexity
Jiafeng Xie and C. Lee ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.

Low register-complexity systolic digit-serial multiplier over GF(2m) based on trinomials
Jiafeng Xie, P. Meher, X. Zhou, and J. Zhang IEEE Trans. Multiscale Computing Systems, vol. 4, no. 4, pp. 773-783, 2018.

Novel hybrid-size digit-serial systolic multiplier over GF(2m)
Z. Hu and Jiafeng Xie Symmetry, vol. 10, no. 11, pp. 1-11, 2018.

Efficient implementation of Karatsuba algorithm based three-operand multiplication over binary extension field
C. Lee, C. Fan, Jiafeng Xie, and S. Yuan IEEE Access, 6: 38234-38242, 2018.

Low complexity implementation of unified systolic multipliers for NIST pentanomials and trinomials over GF(2m)
Q. Shao, Z. Hu, S. Basha, Z. Zhang, Z. Wu, C.Y. Lee, and Jiafeng Xie IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 65, no. 8, pp. 2455-2465, 2018.

Reliable inversion in GF(28) with redundant arithmetic for secure error detection of cryptographic architectures
M. Kermani, A. Jalali, R. Azarderakhsh, Jiafeng Xie, and K.K. R. Choo IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, vol. 37, no. 3, pp. 696-704, 2018.

Low area-delay complexity digit-level parallel-in serial-out multiplier over GF(2m) based on overlap-free Karatsuba algorithm
C. Lee and Jiafeng Xie IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2018.

Efficient FPGA implementation of low-complexity systolic Karatsuba multiplier over GF(2m) based on NIST polynomials
Jiafeng Xie, P.K. Meher, M. Sun, Y. Li, B. Zeng, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 64, no. 7, pp, 1815-1825, 2017.

Low-complexity digit-level systolic Gaussian normal basis multiplier
Q. Shao, Z. Hu, S. Chen, P. Chen, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 25, no. 10, pp. 2817-2827, 2017.

FPGA realization of low register systolic all-one-polynomial multipliers over GF(2m) and their applications in trinomial multipliers
P. Chen, N. Basha, M. Kermani, R. Azarderakhsh, and Jiafeng Xie IEEE Trans. VLSI Systems, vol. 25, no. 9, pp. 725-734, 2017.

Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits
Jiafeng Xie and X. Zhou IEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2017.

DNA-cryptography-based obfuscated systolic finite field multiplier for secure cryptosystem in smart grid
S. Chen, P. Chen, Q. Shao, S. Basha, and Jiafeng Xie Asia Conference on Power and Electrical Engineering (ACPEE), pp. 1-6, 2017.

Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes
M. Kermani, R. Azarderakhsh, and Jiafeng XieIEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2016.

Low-latency high-throughput systolic multipliers over GF(2m) for NIST recommended pentanomials
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 3, pp. 881-890, 2015.

High-throughput digit-level systolic multiplier over GF(2m) based on irreducible trinomials
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 62, no. 5, pp. 481-485, 2015.

High-throughput finite field multipliers using redundant basis for FPGA and ASIC implementations
Jiafeng Xie, P.K. Meher, and Z.-H. Mao IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 1, pp. 110-119, 2015.

Hardware-efficient realization of prime-length DCT based on distributed arithmetic
Jiafeng Xie, J. He, and P.K. Meher IEEE Trans. Computers, vol. 62, no. 6, pp. 1170-1178, 2013.

Low-complexity multiplier for GF(2m) based on all one polynomials
Jiafeng Xie, P.K. Meher, and J. He IEEE Trans. VLSI Systems, vol. 21, no. 1, pp. 168-172, 2013.

Low latency systolic Montgomery multiplier for finite field GF(2m) based on pentanomials
Jiafeng Xie, J. He, and P.K. Meher IEEE Trans. VLSI Systems, vol. 21, no. 2, pp. 385-389, 2013.

FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures
Jiafeng Xie, J. He, and G. Tan Microelectronics Journal (Elsevier), vol. 41, no. 6, pp. 365-370, 2010.

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Awards & Honors

IEEE Philadelphia Section Merrill Buckley Jr. Student Project Award, 2022
Brian Anderson Memorial Award from ECE Department, Villanova University 2022
IEEE Access Outstanding Associate Editor, 2019
IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Best Paper Award, 2019

Resources

You are free to use the resources shared below if used for non-profit purposes or open source projects. Please quote resources in the project from Villanova University Security & Cryptography Lab. :)
The SAC Lab is not responsible for the correctness of the source code.
Github Link: https://github.com/harvestsp

Source code for the polynomial multiplication (Fig. 3) presented in the paper of "Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary Ring-LWE post-quantum cryptography"
Download

Source code for the low complexity and high speed architectures presented in the paper of "Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator"
Download

Source code for the two architectures presented in the paper of "Efficient hardware arithmetic for inverted Binary Ring-LWE based post-quantum cryptography"
Download

Location

  • Tolentine Hall Rm 413
    Electrical and Computer Engineering
    800 Lancaster Avenue
    Villanova, PA 19085

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