Jiafeng (Harvest) Xie
Jiafeng (Harvest) Xie

Assistant Professor
Department of Electrical and Computer Engineering
Villanova University

Location: 413 Tolentine Hall, Department of Electrical and Computer Engineering, Villanova University, Villanova, PA 19085
Email: jiafeng.xie@villanova.edu

Director of Villanova Security and Cryptography (SAC) Lab

Research Interests

Cryptographic Engineering

Post-quantum cryptography related design, implementation and security analysis

Fault Attack and Detection

Novel algorithm-architecture fault attack and detection methodologies for pre-/post-quantum cryptographic circuits

Hardware Security

Hardware IP protection and hardware security primitives for resource-constrained systems

Computer Arithmetic/Digital Design

VLSI digital signal processing and neural network systems design

Villanova Security and Cryptography (SAC) Lab

More Info

Education

University of Pittsburgh, Pittsburgh, PA 01/2013 - 12/2014
Ph.D. in Electrical Engineering

Central South University, Changsha, Hunan, China 09/2007 - 07/2010
M. E. in Control Science and Engineering

Yanshan University, Qinhuangdao, Hebei, China 09/2002 - 07/2006
B. E. in Measurement & Control Technology and Instrumentation

Professional 
Experience

Assistant Professor (tenure-track), Department of Electrical and Computer Engineering, Villanova University, August 2018 - Present

Assistant Professor (tenure-track), Department of Electrical Engineering, Wright State University, January 2015 - July 2018

Research Assistant, Department of Electrical and Computer Engineering, University of Pittsburgh, January 2013 - December 2014. Project: Novel cryptographic circuits for emerging embedded systems security

Research Assistant, School of Information Science and Engineering, Central South University, September 2010 - June 2012. Projects: Hardware efficient implementation of cryptographic circuits and digital signal/image processing systems

Research Assistant, School of Information Science and Engineering, Central South University, September 2007 - June 2010. Project: FPGA-based portable B-ultrasonic diagnosis device

Membership

Senior Member of IEEE (CAS, Computer, and Blockchain Societies)

Member of ACM

Technical Committee Member of IEEE CASCOM

Awards & 
Honors

IEEE Access Outstanding Associate Editor for the year of 2019

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Best Paper Award, 2019

Teaching

Courses
Taught

Instructor at Villanova University
a. ECE-2043/2045 Fundamental Computer Engineering-I Lab
b. ECE-3450 Digital Electronics
c. ECE-3430 Embedded Systems-II
d. ECE-4470 Computer Networks
e. ECE-8440 Hardware System Design & Modeling

Instructor at Wright State University
a. EE-2000 Digital Design with HDL
b. EE-2010 Circuit Analysis I
c. EE-4800/6800 Algorithms to VLSI Architectures
d. EE-8000 VLSI Cryptographic Circuits

Teaching fellow at the University of Pittsburgh
a. Introduction of Electrical Engineering: Circuits and Systems
b. Linear Circuits and System-II
c. Computer Organization
d. Introduction to Image Processing

Thesis
Supervised

Pingxiuqi Chen: FPGA realization of low register systolic all one polynomial multipliers over GF(2m) and their applications in trinomial multipliers

Qiliang Shao: FPGA realization of low register systolic multipliers over GF(2m)

Shaik Nazeem Basha: Novel implementation of finite field multipliers over GF(2m) for emerging cryptographic applications

Independent
Studies
Supervised

Total: 20 students

Spring 2016: Pingxiuqi Chen, Kejin Geng, Anuteja Karru, and Apoorva Narayanappa Masineni

Summer 2016: Santosh Teja Sannidhi

Fall 2016: Bhargav Chary Biroju and Akhileswar Kalari

Spring 2017: Mrudula Adira, Gowtham Cheedepudi, Viraat Donthula, Ravi Teja Duggi, Dinesh Gutta, Balakrishna Jannu, Aneesha Kandi, Vijaya Sai Medasani, Pujitha Nimmagadda, Sahithi Ravilla, and Kranthi Kumar Thummalapally

Summer 2017: Leela Krishna Mohan Potluri

Spring 2021: Elizabeth Carter (Undergraduate Senior, Topic: Hardware Implementation of Polynomial Multiplication for Ring-LWE based PQC)

Advising
Students

Current Ph.D. students: Pengzhou He, Tianyou Bao, and Yazheng Tu

Alumni: Pingxiuqi Chen, Qiliang Shao, Shaik Nazeem Basha

Scholarship

Refereed
Journal
Papers

01. Jiafeng Xie, P. He, X. Wang, and J. Imana, “Efficient hardware implementation of finite field arithmetic AB + C for binary Ring-LWE based post-quantum cryptography,” IEEE Trans. Emerging Topics in Computing, pp. 1-6, 2021.

02. P. He, U. Guin, and Jiafeng Xie, “Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary Ring-LWEpost-quantum cryptography,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp. 1-13, 2021.

03. Jiafeng Xie, C. Lee, P. Meher, and Z.-H. Mao, “Novel bit-parallel and digit-serial systolic finite field multipliers over GF(2m) based on reordered normal basis,” IEEE Trans. VLSI Systems, vol. 27, no. 9, pp. 2119-2130, 2019.

04. J. Pan, C. Lee, A. Sghaier, M. Zeghid, and Jiafeng Xie, “Novel systolization of subquadratic space complexity multipliers based on Toeplitz matrix-vector product approach,” IEEE Trans. VLSI Systems, vol. 27, no. 7, pp. 1614-1622, 2019.

05. C. Lee and Jiafeng Xie, “Digit-serial versatile multiplier based on a novel block recombination of the modified overlap-free Karatsuba algorithm,” IEEE Trans. Circuits and Systems-I, vol. 66, no. 1, pp. 203-214, 2019.

06. Jiafeng Xie, P. Meher, X. Zhou, and J. Zhang, “Low register-complexity systolic digit-serial multiplier over GF(2m) based on trinomials,” IEEE Trans. Multiscale Computing Systems, vol. 4, no. 4, pp. 773-783, 2018.

07. Z. Hu and Jiafeng Xie, “Novel hybrid-size digit-serial systolic multiplier over GF(2m),” Symmetry, vol. 10, no. 11, pp. 1-11, 2018.

08. C. Lee, C. Fan, Jiafeng Xie, and S. Yuan, “Efficient implementation of Karatsuba algorithm based three-operand multiplication over binary extension field,” IEEE Access, 6: 38234-38242, 2018.

09. Q. Shao, Z. Hu, S. Basha, Z. Zhang, Z. Wu, C.Y. Lee, and Jiafeng Xie, “Low complexity implementation of unified systolic multipliers for NIST pentanomials and trinomials over GF(2m),” IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 65, no. 8, pp. 2455-2465, 2018.

10. M. Kermani, A. Jalali, R. Azarderakhsh, Jiafeng Xie, and K.K. R. Choo, “Reliable inversion in GF(28) with redundant arithmetic for secure error detection of cryptographic architectures,” IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, vol. 37, no. 3, pp. 696-704, 2018.

11. Jiafeng Xie, P.K. Meher, M. Sun, Y. Li, B. Zeng, and Z.-H. Mao, “Efficient FPGA implementation of low-complexity systolic Karatsuba multiplier over GF(2m) based on NIST polynomials,” IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 64, no. 7, pp, 1815-1825, 2017.

12. Q. Shao, Z. Hu, S. Chen, P. Chen, and Jiafeng Xie, “Low-complexity digit-level systolic Gaussian normal basis multiplier,” IEEE Trans. VLSI Systems, vol. 25, no. 10, pp. 2817-2827, 2017.

13. P. Chen, N. Basha, M. Kermani, R. Azarderakhsh, and Jiafeng Xie, “FPGA realization of low register systolic all-one-polynomial multipliers over GF(2m) and their applications in trinomial multipliers,” IEEE Trans. VLSI Systems, vol. 25, no. 9, pp. 725-734, 2017.

14. Jiafeng Xie, P.K. Meher, and Z.-H. Mao, “Low-latency high-throughput systolic multipliers over GF(2m) for NIST recommended pentanomials,” IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 3, pp. 881-890, 2015.

15. Jiafeng Xie, P.K. Meher, and Z.-H. Mao, “High-throughput digit-level systolic multiplier over GF(2m) based on irreducible trinomials,” IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 62, no. 5, pp. 481-485, 2015.

16. Jiafeng Xie, P.K. Meher, and Z.-H. Mao, “High-throughput finite field multipliers using redundant basis for FPGA and ASIC implementations,” IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 1, pp. 110-119, 2015.

17. Jiafeng Xie, J. He, and P.K. Meher, “Hardware-efficient realization of prime-length DCT based on distributed arithmetic,” IEEE Trans. Computers, vol. 62, no. 6, pp. 1170-1178, 2013.

18. Jiafeng Xie, P.K. Meher, and J. He, “Low-complexity multiplier for GF(2m) based on all one polynomials,” IEEE Trans. VLSI Systems, vol. 21, no. 1, pp. 168-172, 2013.

19. Jiafeng Xie, J. He, and P.K. Meher, “Low latency systolic Montgomery multiplier for finite field GF(2m) based on pentanomials,” IEEE Trans. VLSI Systems, vol. 21, no. 2, pp. 385-389, 2013.

20. Jiafeng Xie, J. He, and G. Tan, “FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures,” Microelectronics Journal (Elsevier), vol. 41, no. 6, pp. 365-370, 2010.

21. Jiafeng Xie, J. He, and W. Gui, “Low latency systolic multipliers for finite field GF(2m) based on irreducible polynomials,” Journal of Central South University of Technology, vol. 21, no. 5, pp. 1283-1289, 2012.

22. J. He, Jiafeng Xie, and M. He, “Area-efficient systolic multipliers for finite field GF(2m) based on irreducible trinomial,” Journal of Convergence Information Technology, vol. 6, no. 5, pp. 305-313, 2011.

23. J. He and Jiafeng Xie, “Hardware efficient approach for memoryless-based multiplication and its application to FIR filter,” Journal of Computers, vol. 6, no. 11, pp. 2376-2381, 2011.

24. Jiafeng Xie and G. Tan, “Design of B-mode ultrasonic imaging system based on FPGA,” Journal of Zhongyuan University of Technology, vol. 21, no. 2, pp. 72-75, 2010.

25. Jiafeng Xie and G. Tan, “The research on locating the car license in the static image based on MATLAB,” PLC&FA, vol. 6, no. 1, pp. 668-671, 2009.

Conference 
Papers

01. Jiafeng Xie, P. He, and W. Wen, “Efficient implementation of finite field arithmetic for binary Ring-LWE post-quantum cryptography through a novel lookup-table-like method,” Design Automation Conference (DAC), pp. 1-6, 2021

02. Jiafeng Xie, K. Basu, Kris, M. Gaj, and U. Guin, “Special Session: The recent advance of hardware implementation of post-quantum cryptography,” IEEE VLSI Testing Symposium (VTS), pp. 1-10, 2020 (invited).

03. C. Lee and Jiafeng Xie, “Efficient subquadratic space complexity digit-serial multipliers over GF(2m) based on bivariate polynomial basis representation,” Asia and South Pacific Design Automation Conference (ASPDAC), pp. 1-6, 2020.

04. C. Lee and Jiafeng Xie, “Efficient scalable three operand oultiplier over GF(2m) based on novel decomposition strategy,” IEEE International Conference on Computer Design (ICCD), pp. 1-9, 2019.

05. C. Lee and Jiafeng Xie, “High capability and low-complexity: Novel fault detection scheme for finite field multipliers over GF(2m) based on MSPB,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 21-30, 2019 (Best Paper Award).

06. Jiafeng Xie, C. Lee, and P. K. Meher, “Low-complexity systolic multiplier for GF(2m) using Toeplitz Matrix-Vector Product method,” IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

07. Jiafeng Xie and C. Lee, “LSM: Novel low-complexity unified systolic multiplier over binary extension field,” ACM Great Lakes Symposium on VLSI (GLVLSI), 2019.

08. Jiafeng Xie and C. Lee, “Embracing systolic: super systolization of large-scale circulant matrix-vector multiplication on FPGA with subquadratic space complexity,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.

09. C. Lee and Jiafeng Xie, “Low area-delay complexity digit-level parallel-in serial-out multiplier over GF(2m) based on overlap-free Karatsuba algorithm,” IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2018.

10. Jiafeng Xie and X. Zhou, “Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits,” IEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2017.

11. S. Chen, P. Chen, Q. Shao, S. Basha, and Jiafeng Xie, “DNA-cryptography-based obfuscated systolic finite field multiplier for secure cryptosystem in smart grid,” Asia Conference on Power and Electrical Engineering (ACPEE), pp. 1-6, 2017.

12. M. Kermani, R. Azarderakhsh, and Jiafeng Xie, “Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes,” IEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2016.

13. Jiafeng Xie, P.K. Meher, and J. He, “Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing,” IEEE International Symposium on Circuits and Systems-2012, ISCAS-12, pp. 89-92, 2012.

Invited
Talk/Seminar 

Obfuscating systolic-array-based circuits via novel algorithm-to-architecture mapping techniques, Villanova University, 02/15/2018

FPGA implementation of low-complexity systolic Karatsuba multiplier over GF(2m) based on NIST polynomials, Department of Automation, Central South University, 03/17/2017

How to prepare yourself for future career (career center invited seminar), Wright State University, 09/04/2016

Novel single and hybrid finite field multipliers over GF(2m) for emerging cryptographic systems, Wright State University, 07/20/2016

Novel cryptosystem for secure data transmission related to control systems, School of Information Science and Engineering, Central South University, 05/27/2016

Novel finite field multipliers over GF(2m) for emerging cryptographic systems, Department of Electrical Engineering, Wright State University, 10/31/2014

Novel finite field multipliers over GF(2m) for emerging cryptographic systems, Department of Electrical Engineering, University of Michigan, Dearborn, 02/11/2014

Grants
Funded 

NSF SaTC: CORE: Small: Fast Algorithm Originated Fault Detection Scheme for Ring-LWE based Cryptographic Hardware

NIST Efficient Hardware Implementation of Lattice-based Post-Quantum Cryptography

University Travel Grant, Villanova University (spring 2020)

University Travel Grant, Villanova University (spring 2020)

Ohio Department of Higher Education: RAPIDS Grant Phase-II (2017-2019)

Ohio Department of Higher Education: RAPIDS Grant Phase-I (2016-2018)

First-year scholarship fund, Wright State University (2016-2017)

Wireless communication security device fund, Department of Electrical Engineering, Wright State University (2015)

Professional Service

Associate
Editor

IEEE Access (current)

Microelectronics Journal (current)

IEEE Trans. Circuits and Systems-II (previous)

Panel
Reviewer

National Science Foundation SaTC and SCC

Reviewer
for Main-Stream
Journals

Proceedings of the IEEE

IEEE Trans. Industrial Electronics

ACM Journal on Emerging Technologies in Computing Systems

IEEE Trans. Emerging Topics in Computing

IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Circuits and Systems-I

IEEE Trans. Circuits and Systems-II

IEEE Trans. VLSI Systems

IEEE Access

Microelectronics Journal

Microprocessors and Microsystems

Integration, the VLSI

IET Signal Processing

Multidimensional Systems and Signal Processing

Journal of Signal Processing Systems

IET Circuits, Devices & Systems

AEU International Journal of Electronics and Communications

IEEE Transactions on Emerging Topics in Computing

ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Embedded Computing Systems

ACM Journal on Emerging Technologies in Computing Systems

Technical
Committee 
Member/
Reviewer

Hawaii International Conference on System Sciences

IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2019, 2020

IEEE International Conference on Computer Design (ICCD) 2018, 2019

IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2019, 2020

Asia and South Pacific Design Automation Conference (ASP-DAC) 2020

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2020, 2021

Design Automation Conference (DAC) 2020, 2021

GLSVLSI 2021

The International Conference on Hardware/Software Codesign and System

Synthesis (CODES+ISSS) 2021

International Conference On Computer Aided Design (ICCAD) 2021

Session
Chair

IEEE International Conference on Computer Design (ICCD) 2018, 2019 IEEE

International Symposium on Hardware Oriented Security and Trust (HOST) 2020

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