Jiafeng (Harvest) Xie
Jiafeng (Harvest) Xie

Assistant Professor
Department of Electrical and Computer Engineering
Villanova University

Location: 413 Tolentine Hall, Department of Electrical and Computer Engineering, Villanova University, Villanova, PA 19085
Email: jiafeng.xie@villanova.edu

Director of Villanova Security and Cryptography (SAC) Lab

Research Interests

Cryptographic Engineering

Post-quantum cryptography related design, implementation and security analysis

Fault Attack and Detection

Novel algorithm-architecture fault attack and detection methodologies for pre-/post-quantum cryptographic circuits

Hardware Security

Hardware IP protection and hardware security primitives for resource-constrained systems

Computer Arithmetic/Digital Design

VLSI digital signal processing and neural network systems design

Digitalization for Telemetry Systems

New digital design and acceleration techniques for sophisticated aeronautical telemetry systems

Villanova Security and Cryptography (SAC) Lab

More Info

Education

University of Pittsburgh, Pittsburgh, PA 01/2013 - 12/2014
Ph.D. in Electrical Engineering

Central South University, Changsha, Hunan, China 09/2007 - 07/2010
M. E. in Control Science and Engineering

Yanshan University, Qinhuangdao, Hebei, China 09/2002 - 07/2006
B. E. in Measurement & Control Technology and Instrumentation

Professional 
Experience

Assistant Professor (tenure-track), Department of Electrical and Computer Engineering, Villanova University, August 2018 - Present

Assistant Professor (tenure-track), Department of Electrical Engineering, Wright State University, January 2015 - July 2018

Research Assistant/Teaching Fellow, Department of Electrical and Computer Engineering, University of Pittsburgh, January 2013 - December 2014. Project: Novel cryptographic circuits for emerging embedded systems security

Research Assistant, School of Information Science and Engineering, Central South University, September 2010 - June 2012. Projects: Hardware efficient implementation of cryptographic circuits and digital signal/image processing systems

Research Assistant, School of Information Science and Engineering, Central South University, September 2007 - June 2010. Project: FPGA-based portable B-ultrasonic diagnosis device

Membership

Senior Member of IEEE (CAS, Computer, and Blockchain Societies)

Member of ACM

Member of IACR

Technical Committee Member of IEEE CASCOM

Awards & 
Honors

Engineer of the Year Award
IEEE Philadelphia Section, 2024

Art Ryan Award
Department of Electrical and Computer Engineering, Villanova University, 2023

Tenure Track Faculty Career Development Award
College of Engineering, Villanova University, 2023

AFRL VFRP Award and Extension Award
AFRL, Rome, NY, 2022

Merrill Buckley Jr. Student Project Award
IEEE Philadelphia Section, 2022

Brian Anderson Memorial Award
Department of Electrical and Computer Engineering, Villanova University, 2022

Best Paper Award
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019

IEEE Access Outstanding Associate Editor
2019

Teaching

Courses
Taught

Instructor at Villanova University (*: developed by me)
a. ECE–1260 EGR Programming and Applications (designed brand-new slides)
b. ECE-2043/2045 Fundamental Computer Engineering - I Lab
c. ECE–2431 Embedded Systems – I Lab
d. ECE–3430 Embedded Systems – II* (undergraduate course)
e. ECE-3450 Digital Electronics
f. ECE-4470 Computer Networks
g. ECE–5170 Introduction to Post-Quantum Computing* (senior-elective)
e. ECE-8440 Hardware System Design & Modeling* (graduate course)

Instructor at Wright State University
a. EE-2000 Digital Design with HDL
b. EE-2010 Circuit Analysis I
c. EE-4800/6800 Algorithms to VLSI Architectures
d. EE-8000 VLSI Cryptographic Circuits

Teaching fellow at the University of Pittsburgh
a. Introduction of Electrical Engineering: Circuits and Systems
b. Linear Circuits and System-II
c. Computer Organization
d. Introduction to Image Processing

Thesis
Supervised

Elizabeth Carter: Efficient polynomial multiplication hardware accelerators for lattice-based post-quantum cryptography

Pingxiuqi Chen: FPGA realization of low register systolic all one polynomial multipliers over GF(2m) and their applications in trinomial multipliers

Qiliang Shao: FPGA realization of low register systolic multipliers over GF(2m)

Shaik Nazeem Basha: Novel implementation of finite field multipliers over GF(2m) for emerging cryptographic applications

Independent
Studies
Supervised
(Recent ones)

Spring 2024: Sam Coulon

Spring 2021: Elizabeth Carter (Undergraduate Senior, Topic: Hardware Implementation of Polynomial Multiplication for Ring-LWE based PQC)

Advising
Students

Current Ph.D. students: Pengzhou He, Tianyou Bao, and Yazheng Tu

Current M.S. and B.S. students: Sam Coulon, Ben Mongirdas, and Victor Xu

High-school seniors: Antonio Fiorentino Wong and Christopher Lin

Alumni: Elizabeth Carter (M.S. Thesis)

Capstone
Senior Design
Project

2023 – 2024: Jorge Ramos Putz, Kennedy Cornish (still ongoing)

2022 – 2023: Sam Coulon, Duncun Smith, Sean Garner, and Robert Rotyliano (Art Ryan Award)

2021 – 2022: Benjamin J. Lucas, Ali Alwan, Marion Murzello, Andrew J. Schwartz, David Guevara (Brian Anderson Memorial Award)

Scholarship

Refereed
Journal
Papers

Jiafeng Xie, W. Zhao, H. Lee, D. B. Roy, and X. Zhang, “Hardware circuits and systems design for post-quantum cryptography – A tutorial brief,” IEEE Trans. Circuits and Systems II, pp.1-7, 2024.

P. He, S. C. Oliva Madrigal, C¸ . K. Koc¸, T. Bao, and Jiafeng Xie, “CASA: A compact and scalable accelerator for approximate homomorphic encryption,” IACR Transactions on Cryptographic Hardware and Embedded Systems(TCHES), vol. 2024, no. 2, pp. 1-30, 2024.

T. Bao, P. He, S. Bai, and Jiafeng Xie, “TINA: TMVP initiated novel accelerator for lightweight Ring-LWE-based PQC,” IEEE Trans. VLSI Systems, pp. 1-12, 2023.

T. Bao, P. He, Jiafeng Xie, and H S. Jacinto, “AEKA: FPGA implementation of area-efficient Karatsuba accelerator for Ring-Binary-LWE-based lightweight PQC,” ACM Trans. Reconfigurable Technology and Systems, pp. 1-22, 2023 (FPT’23-Journal Track).

P. He, T. Tu, Jiafeng Xie, and H S. Jacinto, “KINA: Karatsuba initiated novel accelerator for Ring-Binary-LWE (RBLWE)-based post-quantum cryptography,” IEEE Trans. VLSI Systems, vol. 31, no. 10, pp. 1551-1564, 2023.

P. He, T. Tu, C¸ . K. Koc¸, and Jiafeng Xie, “Hardware-implemented lightweight accelerator for large integer polynomial multiplication,” IEEE Computer Architecture Letters, vol. 22, no. 1, pp. 57-60, 2023 (popular paper in IEEE Xplore).

Y. Tu, P. He, C¸ .K. Koc¸, and Jiafeng Xie, “LEAP: Lightweight and efficient accelerator for sparse polynomial multiplication of HQC,” IEEE Trans. VLSI Systems, vol. 31, no. 6, pp. 892-896, 2023.

P. He, Y. Tu, T. Bao, L. Sousa, and Jiafeng Xie, “COPMA: Compact and optimized polynomial multiplier acceleratorfor high-performance implementation of LWR-based PQC,” IEEE Trans. VLSI Systems, vol. 31, no. 4, pp. 596-600, 2023.

P. He, T. Bao, Jiafeng Xie, and M. Amin, “FPGA implementation of compact hardware accelerators for Ring-Binary-LWE based post-quantum cryptography,” ACM Trans. Reconfigurable Technology and Systems, vol. 15, no.3, pp. 1-23, 2022 (FPT’22-Journal Track).

Y. Zhong, A. Jain, M.T. Rahman, N. Adadi, Jiafeng Xie, and U. Guin, ”AFIA: ATPG-guided fault injection attack on secure logic locking,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 38, pp. 527–546, 2022.

J. Imãna*, P. He*, T. Bao, Y. Tu, and Jiafeng Xie, “Efficient hardware arithmetic for inverted Binary Ring-LWE based post-quantum cryptography,” IEEE Trans. Circuits and Systems-I, 2022 (*: equal contribution).

B. J. Lucas, A. Alwan, M. Murzello, Y. Tu, P. He, A. J. Schwartz, D. Guevara, U. Guin, K. Juretus, and Jiafeng Xie, “Lightweight hardware implementation of binary Ring-LWE PQC accelerator,” IEEE Computer Architecture Letters, 2022.(popular paper in IEEE Xplore)

C. -Y. Lee, M. Zeghid, A. Sghaier, H. Y. Ahmed and Jiafeng Xie, "Efficient hardware implementation of large field-size Elliptic Curve Cryptographic processor," IEEE Access, 2022.

S. Hussain, S. Ullah, I. Ali, Jiafeng Xie, and V. Inukollu, “Certificateless signature schemes in industrial Internet of Things: A comparative survey,” Computer Communications, vol. 181, pp. 116-131, 2022.

Jiafeng Xie, P. He, X. Wang, and J. Imana, “Efficient hardware implementation of finite field arithmetic AB + C for binary Ring-LWE based post-quantum cryptography,” IEEE Trans. Emerging Topics in Computing, vol. 10, no. 2, pp. 1222-1228, 2022.

P. He, U. Guin, and Jiafeng Xie, “Novel low-complexity polynomial multiplication over hybrid fields for efficient implementation of binary Ring-LWEpost-quantum cryptography,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp. 1-13, 2021.

Jiafeng Xie, C. Lee, P. Meher, and Z.-H. Mao, “Novel bit-parallel and digit-serial systolic finite field multipliers over GF(2m) based on reordered normal basis,” IEEE Trans. VLSI Systems, vol. 27, no. 9, pp. 2119-2130, 2019.

J. Pan, C. Lee, A. Sghaier, M. Zeghid, and Jiafeng Xie, “Novel systolization of subquadratic space complexity multipliers based on Toeplitz matrix-vector product approach,” IEEE Trans. VLSI Systems, vol. 27, no. 7, pp. 1614-1622, 2019.

C. Lee and Jiafeng Xie, “Digit-serial versatile multiplier based on a novel block recombination of the modified overlap-free Karatsuba algorithm,” IEEE Trans. Circuits and Systems-I, vol. 66, no. 1, pp. 203-214, 2019.

Jiafeng Xie, P. Meher, X. Zhou, and J. Zhang, “Low register-complexity systolic digit-serial multiplier over GF(2m) based on trinomials,” IEEE Trans. Multiscale Computing Systems, vol. 4, no. 4, pp. 773-783, 2018.

Z. Hu and Jiafeng Xie, “Novel hybrid-size digit-serial systolic multiplier over GF(2m),” Symmetry, vol. 10, no. 11, pp. 1-11, 2018.

C. Lee, C. Fan, Jiafeng Xie, and S. Yuan, “Efficient implementation of Karatsuba algorithm based three-operand multiplication over binary extension field,” IEEE Access, 6: 38234-38242, 2018.

Q. Shao, Z. Hu, S. Basha, Z. Zhang, Z. Wu, C.Y. Lee, and Jiafeng Xie, “Low complexity implementation of unified systolic multipliers for NIST pentanomials and trinomials over GF(2m),” IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 65, no. 8, pp. 2455-2465, 2018.

M. Kermani, A. Jalali, R. Azarderakhsh, Jiafeng Xie, and K.K. R. Choo, “Reliable inversion in GF(28) with redundant arithmetic for secure error detection of cryptographic architectures,” IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, vol. 37, no. 3, pp. 696-704, 2018.

Jiafeng Xie, P.K. Meher, M. Sun, Y. Li, B. Zeng, and Z.-H. Mao, “Efficient FPGA implementation of low-complexity systolic Karatsuba multiplier over GF(2m) based on NIST polynomials,” IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 64, no. 7, pp, 1815-1825, 2017.

Q. Shao, Z. Hu, S. Chen, P. Chen, and Jiafeng Xie, “Low-complexity digit-level systolic Gaussian normal basis multiplier,” IEEE Trans. VLSI Systems, vol. 25, no. 10, pp. 2817-2827, 2017.

P. Chen, N. Basha, M. Kermani, R. Azarderakhsh, and Jiafeng Xie, “FPGA realization of low register systolic all-one-polynomial multipliers over GF(2m) and their applications in trinomial multipliers,” IEEE Trans. VLSI Systems, vol. 25, no. 9, pp. 725-734, 2017.

Jiafeng Xie, P.K. Meher, and Z.-H. Mao, “Low-latency high-throughput systolic multipliers over GF(2m) for NIST recommended pentanomials,” IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 3, pp. 881-890, 2015.

Jiafeng Xie, P.K. Meher, and Z.-H. Mao, “High-throughput digit-level systolic multiplier over GF(2m) based on irreducible trinomials,” IEEE Trans. Circuits & Systems-II: Express Briefs, vol. 62, no. 5, pp. 481-485, 2015.

Jiafeng Xie, P.K. Meher, and Z.-H. Mao, “High-throughput finite field multipliers using redundant basis for FPGA and ASIC implementations,” IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 62, no. 1, pp. 110-119, 2015.

Jiafeng Xie, J. He, and P.K. Meher, “Hardware-efficient realization of prime-length DCT based on distributed arithmetic,” IEEE Trans. Computers, vol. 62, no. 6, pp. 1170-1178, 2013.

Jiafeng Xie, P.K. Meher, and J. He, “Low-complexity multiplier for GF(2m) based on all one polynomials,” IEEE Trans. VLSI Systems, vol. 21, no. 1, pp. 168-172, 2013.

Jiafeng Xie, J. He, and P.K. Meher, “Low latency systolic Montgomery multiplier for finite field GF(2m) based on pentanomials,” IEEE Trans. VLSI Systems, vol. 21, no. 2, pp. 385-389, 2013.

Jiafeng Xie, J. He, and G. Tan, “FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures,” Microelectronics Journal (Elsevier), vol. 41, no. 6, pp. 365-370, 2010.

Jiafeng Xie, J. He, and W. Gui, “Low latency systolic multipliers for finite field GF(2m) based on irreducible polynomials,” Journal of Central South University of Technology, vol. 21, no. 5, pp. 1283-1289, 2012.

J. He, Jiafeng Xie, and M. He, “Area-efficient systolic multipliers for finite field GF(2m) based on irreducible trinomial,” Journal of Convergence Information Technology, vol. 6, no. 5, pp. 305-313, 2011.

J. He and Jiafeng Xie, “Hardware efficient approach for memoryless-based multiplication and its application to FIR filter,” Journal of Computers, vol. 6, no. 11, pp. 2376-2381, 2011.

Jiafeng Xie and G. Tan, “Design of B-mode ultrasonic imaging system based on FPGA,” Journal of Zhongyuan University of Technology, vol. 21, no. 2, pp. 72-75, 2010.

Jiafeng Xie and G. Tan, “The research on locating the car license in the static image based on MATLAB,” PLC&FA, vol. 6, no. 1, pp. 668-671, 2009.

Conference 
Papers

Samuel Coulon, Pengzhou He, Tianyou Bao, Jiafeng Xie, “Efficient hardware RNS decomposition for postquantum signature scheme FALCON,” 57th Asilomar Conference on Signals, Systems, and Computers, pp. 1-8, 2023.

P. He*, T. Bao*, Y. Tu, and Jiafeng Xie, “Efficient implementation of Ring-Binary-LWE-based lightweight PQC accelerator on the FPGA platform,” IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2023), pp. 114-120, 2023 (*: equal contribution).

P. He, Y. Tu, and Jiafeng Xie, “LOCS: Low-latency and constant-timing implementation of fixed-weight sampler for HQC,” IEEE International Symposium on Circuits and Systems-2023 (ISCAS’23), pp. 1-5, 2023.

P. He and J. Xie, “Novel Implementation of High-performance polynomial multiplication for unified KEM Saber based on TMVP design strategy,” International Symposium on Quality Electronic Design (ISQED), pp. 1-8, 2023.

P. He, T. Bao, Y. Tu and Jiafeng Xie, “HPMA-Saber: High-performance polynomial multiplication accelerator for KEM Saber,” IEEE International Conference on Computer Design (ICCD), pp. 525-528, 2022.

P. He, Y. Tu, A. Khalid, M. O’Neil, and Jiafeng Xie, “HPMA-NTRU: High-performance polynomial multiplication accelerator for NTRU,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’22), pp. 1-6, 2022.

T. Bao, J. L. Im˜ana, P. He and Jiafeng Xie, “Work-in-Progress: High-performance systolic hardware accelerator for RBLWE-based post-quantum cryptography,” CODES+ISSS, pp. 5-6, 2022.

T. Bao, P. He, and Jiafeng Xie, “Systolic acceleration of polynomial multiplication for KEM Saber and binary Ring-LWE post-quantum cryptography,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2022.

Y. Tu, P. He, C. Lee, D. Chasaki, and Jiafeng Xie, “Hardware implementation of high-performance polynomial multiplication for KEM Saber,” IEEE International Symposium on Circuits and Systems-2022 (ISCAS’22).

Y. Tu, P. He, U. Guin, and Jiafeng Xie, “Low-complexity implementation of lightweight Ring-LWE based post-quantum cryptography,” GOMACTech, pp. 1-6, 2022 (accepted for presentation).

Jiafeng Xie, P. He, and T. Bao, “Ultra low-complexity implementation of binary Ring-LWE based post-quantum cryptography on FPGA platform,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2022, (poster).

Jiafeng Xie, P. He, and C.Y. Lee, “CROP: FPGA implementation of high-performance polynomial multiplication in Saber KEM based on novel cyclic-row oriented processing strategy,” IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2021.

P. He, C. Lee, and Jiafeng Xie, “Compact coprocessor for KEM Saber: novel scalable matrix originated processing,” NIST Third PQC Standardization Conference, pp. 1-16, 2021.

Jiafeng Xie, P. He, and W. Wen, “Efficient implementation of finite field arithmetic for binary Ring-LWE post-quantum cryptography through a novel lookup-table-like method,” Design Automation Conference (DAC), pp. 1-6, 2021.

Jiafeng Xie, K. Basu, Kris, M. Gaj, and U. Guin, “Special Session: The recent advance of hardware implementation of post-quantum cryptography,” IEEE VLSI Testing Symposium (VTS), pp. 1-10, 2020 (invited).

C. Lee and Jiafeng Xie, “Efficient subquadratic space complexity digit-serial multipliers over GF(2m) based on bivariate polynomial basis representation,” Asia and South Pacific Design Automation Conference (ASPDAC), pp. 1-6, 2020.

C. Lee and Jiafeng Xie, “Efficient scalable three operand oultiplier over GF(2m) based on novel decomposition strategy,” IEEE International Conference on Computer Design (ICCD), pp. 1-9, 2019.

C. Lee and Jiafeng Xie, “High capability and low-complexity: Novel fault detection scheme for finite field multipliers over GF(2m) based on MSPB,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 21-30, 2019 (Best Paper Award).

Jiafeng Xie, C. Lee, and P. K. Meher, “Low-complexity systolic multiplier for GF(2m) using Toeplitz Matrix-Vector Product method,” IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

Jiafeng Xie and C. Lee, “LSM: Novel low-complexity unified systolic multiplier over binary extension field,” ACM Great Lakes Symposium on VLSI (GLVLSI), 2019.

Jiafeng Xie and C. Lee, “Embracing systolic: super systolization of large-scale circulant matrix-vector multiplication on FPGA with subquadratic space complexity,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.

C. Lee and Jiafeng Xie, “Low area-delay complexity digit-level parallel-in serial-out multiplier over GF(2m) based on overlap-free Karatsuba algorithm,” IEEE International Conference on Computer Design (ICCD), pp. 1-8, 2018.

Jiafeng Xie and X. Zhou, “Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits,” IEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2017.

S. Chen, P. Chen, Q. Shao, S. Basha, and Jiafeng Xie, “DNA-cryptography-based obfuscated systolic finite field multiplier for secure cryptosystem in smart grid,” Asia Conference on Power and Electrical Engineering (ACPEE), pp. 1-6, 2017.

M. Kermani, R. Azarderakhsh, and Jiafeng Xie, “Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes,” IEEE Asian Hardware Orientated Security and Trust Symposium (Asian HOST), pp. 1-6, 2016.

D.V. Penumetcha, Jiafeng Xie, and S. Ren, “FPGA design space exploration of IDEA cryptography IP core”, IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, 2015.

Jiafeng Xie, P.K. Meher, and J. He, “Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing,” IEEE International Symposium on Circuits and Systems-2012, ISCAS-12, pp. 89-92, 2012.

Others

What is The Recent Advance in Post-Quantum Cryptography?
Jiafeng Xie, SIGDA Electronic Newsletter, “What is” Column, May 2021. [Online]. Available: https://www.sigda.org/publications/newsletter/

Invited
Talk/Seminar 

Design and Implementation of Lightweight Post-Quantum Cryptography: From Algorithmic Derivation to Architectural Innovation, University of New Hampshire, NH, 10/20/2023

Hardware Acceleration for Post-Quantum Cryptography: Algorithmic Derivation, and Architectural Innovation, Temple University, Philadelphia, PA, 9/27/2023

Hardware Acceleration for Post-Quantum Cryptography: Algorithmic Derivation, and Architectural Innovation, Florida Atlantic University, Boca Raton, FL,12/14/2022

Hardware acceleration for post-quantum cryptography: recent advance, algorithmic derivation, and architectural innovation, AFRL, Rome, NY, 7/7/2022

Obfuscating systolic-array-based circuits via novel algorithm-to-architecture mapping techniques, Villanova University, 02/15/2018

FPGA implementation of low-complexity systolic Karatsuba multiplier over GF(2m) based on NIST polynomials, Department of Automation, Central South University, 03/17/2017

How to prepare yourself for future career (career center invited seminar), Wright State University, 09/04/2016

Novel single and hybrid finite field multipliers over GF(2m) for emerging cryptographic systems, Wright State University, 07/20/2016

Novel cryptosystem for secure data transmission related to control systems, School of Information Science and Engineering, Central South University, 05/27/2016

Novel finite field multipliers over GF(2m) for emerging cryptographic systems, Department of Electrical Engineering, Wright State University, 10/31/2014

Novel finite field multipliers over GF(2m) for emerging cryptographic systems, Department of Electrical Engineering, University of Michigan, Dearborn, 02/11/2014

Grants
Funded 

Delta Information Systems, Inc., Space-Time Coding for Aeronautical Telemetry

NSF SaTC: CORE: Small: Fast Algorithm Originated Fault Detection Scheme for Ring-LWE based Cryptographic Hardware

NIST Efficient Hardware Implementation of Lattice-based Post-Quantum Cryptography

Tenure Track Faculty Career Development Award 2023, College of Engineering, Villanova University

Villanova Institute for Research and Scholarship Small Research Grant 2023

Villanova University Summer Grant Program 2022

University Travel Grant, Villanova University (Spring 2019, Spring 2020, Fall 2021, Spring 2023)

Ohio Department of Higher Education: RAPIDS Grant Phase-II (2017-2019)

Ohio Department of Higher Education: RAPIDS Grant Phase-I (2016-2018)

First-year scholarship fund, Wright State University (2016-2017)

Wireless communication security device fund, Department of Electrical Engineering, Wright State University (2015)

Professional Service

Senior Associate
Editor

IEEE Trans. Circuits and Systems-II (2024 – )

Associate
Editor

IEEE Trans. VLSI Systems (2023 – )

IEEE Access (2017 – )

Microelectronics Journal (2016 – )

IEEE Trans. Circuits and Systems-II (2020)

Conference
Organizing
Committee

Microelectronics Competition Co-Chair for IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2022)

AV Chair for IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2023 - 2024)

Panel
Reviewer

National Science Foundation SaTC and SCC

Reviewer
for Main-Stream
Journals

Proceedings of the IEEE

IEEE Trans. Industrial Electronics

IEEE Trans. Emerging Topics in Computing

IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems

IEEE Trans. Circuits and Systems-I: Regular Papers

IEEE Trans. Circuits and Systems-II: Express Briefs

IEEE Trans. VLSI Systems

IEEE Access

IEEE Circuits and Systems Magazine

Microelectronics Journal

Microprocessors and Microsystems

Integration, the VLSI

IET Signal Processing

Multidimensional Systems and Signal Processing

Journal of Signal Processing Systems

IET Circuits, Devices & Systems

AEU International Journal of Electronics and Communications

ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Embedded Computing Systems

ACM Journal on Emerging Technologies in Computing Systems

Technical
Committee 
Member/
Reviewer

IEEE International Symposium on Circuits and Systems (ISCAS) (2020 - 2024)

IEEE International Conference on Computer Design (ICCD) (2018 - 2019, 2022 - 2023)

IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2019 - 2021)

Asia and South Pacific Design Automation Conference (ASP-DAC) (2020)

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2020 - 2024)

Design Automation Conference (DAC) (2020 - 2022)

GLSVLSI (2021 - 2023)

The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (2021 - 2022)

International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) (2023)

International Conference On Computer Aided Design (ICCAD) (2021 - 2023)

Top Picks in Hardware and Embedded Security (2021)

IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2022)

IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (2022)

International Conference on Field Programmable Technology (FPT) (2022 - 2023)

ARITH (2022 - 2024)

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2023)

IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) (2022 - 2024)

Session
Chair

IEEE International Conference on Computer Design (ICCD) (2018 - 2019)

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2020, 2022 - 2023)

Top Picks in Hardware and Embedded Security (2021)

Design Automation Conference (DAC) (2021)

IEEE International Symposium on Circuits and Systems (ISCAS) (2022 - 2023)

ARITH (2022)

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2022)

International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (2022)

International Conference on Field-Programmable Technology (FPT) (2023)

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